参数资料
型号: XRT8001IP-F
厂商: Exar Corporation
文件页数: 22/48页
文件大小: 0K
描述: IC WAN CLOCK E1/E1 DUAL 18PDIP
产品变化通告: XRT obsolescence 05/Mar/2012
标准包装: 41
类型: 时钟/频率发生器
PLL:
主要目的: 以太网(WAN),T1/E1
输入: 时钟
输出: 时钟
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 无/无
频率 - 最大: 16.384kHz
电源电压: 3.3 V ~ 5 V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 18-DIP(0.300",7.62mm)
供应商设备封装: 18-PDIP
包装: 管件
XRT8001
29
Rev. 1.01
Figure 17. Illustration of the XRT8001 WAN Clock
Operating in the “High Speed – Reverse” Mode
6.7 Configuring the XRT8001 WAN Clock into the
“High Speed – Reverse” Mode.
The user can configure the XRT8001 WAN Clock to
operate in the “High Speed – Reverse” Mode, by
executing the following steps.
Step 1 – Configure the XRT8001 to operate in the
“SLAVE” Mode, by pulling the “MSB” input pin (pin 8)
to GND.
Step 2 - Write the value "1101" into bts D4-D1 within
command register CR0
Note: If the user wishes to output a clock signal via the
CLK1 output signal, then he/she should also write a “1” into
the “PL1EN” bit-field within Command Register CR0.
This step configures the XRT8001 to operate in the
“High Speed – Reverse” Mode.
Step 3 – Write the binary expression “0000” into bit-
fields “D4 through D1” within Command Register, CR1,
as illustrated below.
Note: If the user wishes to output a clock signal via the
CLK2 output signal, then he/she should also write a “1” into
the “PL2EN” bit-field within Command Register CR1.
Step 4 – Specify the value for “M” (e.g., as in the “M x
2.048MHz” clock signal) which is to be output via the
“CLK1” output pin.
This is accomplished by reviewing Table 7, and deter-
mining the 5 bit binary value which corresponds with
the desired value of “M”. Afterwards, the user should
write this value into Command Register CR2.
Command Register, CR1 (Address = 0x01)
D4
D3
D2
D1
D0
M4
M3
M2
M1
PL2EN
0
1
Command Register CR0 (Address = 0x00)
D4
D3
D2
D1
D0
IOC4
IOC3
IOC2
IOC1
PL1EN
1
1
0
1
X
XRT8001
WAN Clock
FIN
CLK1
CLK2
64kHz
M x 2.048MHz
M = 1, 2, 4 or 8
M x 2.048MHz
M = 1, 2, 4 or 8
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