参数资料
| 型号： | XRT82L24AIV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 22/39页 |
| 文件大小： | 0K |
| 描述： | IC LIU E1 QAUD 100TQFP |
| 标准包装： | 90 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 4/4 |
| 规程： | E1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | XRT82L24AIV-F-ND |
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
27
TABLE 12: CHANNEL STATUS REGISTER
CHANNEL STATUS REGISTER
PARALLEL PORT ADDRESS CHANNEL 0: 0010
PARALLEL PORT ADDRESS CHANNEL 1: 0101
PARALLEL PORT ADDRESS CHANNEL 2: 1000
PARALLEL PORT ADDRESS CHANNEL 3: 1011
BIT NO.SYMBOL
FUNCTION
REGISTER
TYPE
RESET
VALUE
7DMOn
Driver Monitor Output:
This bit is set to a "1" to indicate current DMO is detected. Any change in the
state of this bit causes an interrupt to be generated. Reading this register bit
does not clear the DMO bit.
R0
6LOSn
Loss of Signal:
This bit is set to a "1" to indicate current LOS condition is detected. Any
change in the state of this bit causes an interrupt to be generated. Reading
this register bit does not clear the LOS bit.
R0
5
LCVn
Line Code Violation:
This bit is set to a "1" to indicate current LCV condition is detected. Any
change in the state of this bit causes an interrupt to be generated. Reading
this register bit does not clear the LCV bit.
R0
4TCKLn
Transmit Clock Loss:
This bit is set to a "1" to indicate current TxClk clock loss is detected. Any
change in the state of this bit causes an interrupt to be generated. Reading
this register bit does not clear the TCKL bit.
R0
3DMOnIS Driver Monitor Output:
This bit is set to a "1" every time the state of DMO status changes since last
read. This bit is cleared by a read operation.
RUR
0
2LOSnIS
Latched- Loss of signal:
This bit is set to a "1" every time the state of LOS changes since last read.
This bit is cleared by a read operation.
RUR
0
1LCVnIS
Latched- Line Code Violation:
This bit is set to a "1" every time the state of LCV changes since last read.
This bit is cleared by a read operation.
RUR
0
0TCLKnIS Latched-Transmit Clock Loss.
This bit is set to a "1" every time the state of TCKL changes since last read.
This bit is cleared by a read operation.
RUR
0
NOTE: n = channel number 0 to 3.
NOTE: Register Type Abrbreviation:
R = Read Only, R/W = Read or Write, RUR = Reset Upon Read
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT82L24ES | 功能描述:界面开发工具 Evaluation Board for XRT82L24 Series RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XRT82L24IV | 制造商:EXAR 制造商全称:EXAR 功能描述:QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT82L34IV | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Interface IC |
| XRT83D10 | 制造商:EXAR 制造商全称:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10ES | 功能描述:外围驱动器与原件 - PCI 1 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
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