参数资料
型号: XRT83SL30IV-F
厂商: Exar Corporation
文件页数: 76/76页
文件大小: 0K
描述: IC LIU T1/E1/J1 SGL 64TQFP
标准包装: 160
类型: 线路接口装置(LIU)
驱动器/接收器数: 1/1
规程: T1,E1,J1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(10x10)
包装: 托盘
XRT83SL30
6
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
RECEIVER
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
RLOS
63
O
Receiver Loss of Signal
This signal is asserted ‘High’ for at least one RCLK cycle to indicate loss of
signal at the receive input. RLOS will remain “High” for the entire duration of
the loss of signal detected by the receiver logic.
RCLK
64
O
Receiver Clock Output
RNEG
LCV
1
O
Receiver Negative Data Output
In dual-rail mode, this signal is the receiver negative-rail output data.
Line Code Violation Output
In single-rail mode, this signal goes ‘High’ for one RCLK cycle to indicate a
code violation is detected in the received data. If AMI coding is selected,
every bipolar violation received will cause this pin to go “High”.
RPOS
RDATA
2
O
Receiver Positive Data Output
In dual-rail mode, this signal is the receive positive-rail output data sent to the
Framer.
Receiver NRZ Data Output
In single-rail mode, this signal is the receive NRZ format output data sent to
the Framer.
RTIP
4
I
Receiver Differential Tip Positive Input
Positive differential receive input from the line.
RRING
5
I
Receiver Differential Ring Negative Input
Negative differential receive input from the line.
RXMUTE
50
I
Receive Muting
In Hardware Mode, connect this pin ‘High’ to mute RPOS and RNEG out-
puts to a “Low” state upon receipt of LOS condition to prevent data chatter-
ing. Connect this pin to ‘Low’ to disable muting function.
NOTE: Internally pulled “Low” with 50k
resistor.
RCLKE
53
I
Receive Clock Edge
In Hardware Mode, with this pin set to ‘High’ the output receive data is
updated on the falling edge of RCLK. With this pin tied ‘Low’, output data is
updated on the rising edge of RCLK.
NOTE: Internally pulled “Low” with a 50k
resistor.
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