参数资料
型号: XRT91L32IQ-F
厂商: Exar Corporation
文件页数: 11/37页
文件大小: 0K
描述: IC TXRX SONET/SDH 8BIT 100QFP
标准包装: 20
类型: 收发器
规程: SONET/SDH
电源电压: 3.3V
安装类型: 表面贴装
封装/外壳: 100-BQFP
供应商设备封装: 100-QFP(14x20)
包装: 托盘
其它名称: 1016-1489
XRT91L32IQ-F-ND
xr
XRT91L32
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
17
2.6
SONET Frame Boundary Detection and Byte Alignment Recovery
A Frame and Byte Boundary Detection circuit searches the incoming data channel for three consecutive A1
(0xF6 Hex) bytes followed by three consecutive A2 (0x28 Hex) bytes. The detector operates under the control
of the OOF (Out of Frame) signals provided from the SONET Framer. Detection is enabled when OOF is held
"High" and remains active until OOF goes "Low." When framing pattern detection is enabled, the framing
pattern is used to locate byte and frame boundaries in the incoming receive data stream. The receive serial-to-
parallel converter block uses the located byte boundary to assemble the incoming data stream into bytes for
output on the parallel data output bus RXDO[7:0]. The frame boundary is reported on the frame pulse
(FRAMEPULSE) output at the onset of detecting the third A2 byte pattern when any serial 48-bit pattern
matching the framing pattern is detected on the incoming data stream. While in the pattern search and
detection state and so long is OOF is active, the frame pulse (FRAMEPULSE) output is activated for one byte
clock cycle (RXPCLKO = 12.86 ns pulse duration for STS-12/STM-4 or 51.44 ns pulse duration for STS-3/
STM-1) anytime a 48-bit pattern matching the framing pattern is detected on the incoming data stream. Once
the SONET Framer Overhead Circuitry has verified that frame and byte synchronization are correct, the OOF
input pin should be de-asserted by the SONET Framer to disable the XRT91L32 frame search process from
trying to synchronize repeatedly and to de-activate FRAMEPULSE. When the XRT91L32’s framing pattern
detection is disabled upon the de-assertion of OOF input pin from the SONET Framer, the byte boundary will
lock to the detected location and will remain locked to that location found when detection was previously
enabled.
2.7
Receive Serial Input to Parallel Output (SIPO)
During STS-12/STM-4 operation, the SIPO is used to convert the 622.08 Mbps serial data input to 77.76 Mbps
parallel data output which can interface to a SONET Framer/ASIC. If the XRT91L32 is operating in STS-3/
STM-1, the SIPO will convert the 155.52 Mbps serial data input to 19.44 Mbps parallel data output. The SIPO
bit de-interleaves the serial data input into an 8-bit parallel output to RXDO[7:0]. A simplified block diagram is
shown in Figure 8. XRT91L32 clocks data out on RXDO[7:0] at the falling edge of RXPCLKO.
FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO
b00
b01
b02
b03
bn0
bn1
bn2
bn3
bn+0
bn+1
bn+2
bn+3
b70
b71
b72
b73
8-bit Parallel LVTTL Output Data
RXDO0
RXDO7
RXDOn+
RXDOn
RXIP/N
RXPCLKO
b30b20b10b00
b70b60b50b40
b33b23b13
b43
b53
b63
b73
SI
PO
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
622.08 Mbps STS-12/STM-4 or
155.52 Mbps STS-3/STM-1 serial data rate
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