参数资料
型号: XRT91L34IVTR-F
厂商: Exar Corporation
文件页数: 24/38页
文件大小: 0K
描述: IC MULTIRATE CDR QUAD 128LQFP
标准包装: 750
类型: 时钟和数据恢复(CDR),扇出缓冲器(分配),多路复用器
PLL:
主要目的: SONET/SDH,STS,STM
输入: LVDS,LVPECL
输出: LVDS,LVPECL
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 是/是
频率 - 最大: 622.08MHz
电源电压: 1.71 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x14)
包装: 带卷 (TR)
XRT91L34
30
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
CHANNELIZED REGISTERS
NOTE: n denotes channel number.
TABLE 15: MICROPROCESSOR INTERFACE REGISTER 0X08, 0X10, 0X18, 0X20 BIT DESCRIPTION
CHANNEL CONTROL REGISTER (CH0 = 0X08, CH1 = 0X10, CH2 = 0X18, CH3 = 0X20)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
RO
0
D6
Reserved
This Register Bit is Not Used
RO
0
D5
Reserved
This Register Bit is Not Used
RO
0
D4
Reserved
This Register Bit is Not Used
RO
0
D3
Reserved
This Register Bit is Not Used
RO
0
D2
RCLKDISn
Recovered Serial Clock Output Disable
This bit is used to control the activity of the 622.08/155.52/51.84
MHz differential serial clock output. Tristating RXCLKOnP/N output
reduces power consumption.
"0" = RXCLKOnP/N output Enabled
"1" = RXCLKOnP/N output Tristated
R/W
0
D1
CDRDISn
Clock and Data Recovery Unit Disable
Disables Internal Clock and Data Recovery Unit.
"0" = Internal CDR Unit is Enabled
"1" = Internal CDR Unit is Disabled
R/W
0
D0
POLn
Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"0" = SDEXT is active "Low"
"1" = SDEXT is active "High"
R/W
0
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