参数资料
| 型号： | XRT91L34IVTR-F |
| 厂商： | Exar Corporation |
| 文件页数： | 9/38页 |
| 文件大小： | 0K |
| 描述： | IC MULTIRATE CDR QUAD 128LQFP |
| 标准包装： | 750 |
| 类型： | 时钟和数据恢复（CDR），扇出缓冲器（分配），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STS，STM |
| 输入： | LVDS，LVPECL |
| 输出： | LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622.08MHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-LQFP（14x14） |
| 包装： | 带卷 (TR) |
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XRT91L34
17
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
2.4
Internal Digital Loss of Signal and External Signal Detection
XRT91L34 has an integrated Digital Loss of Signal (DLOS) circuit and supports external Signal Detection
(SDEXT) for detecting and determining received signal integrity. The internal DLOS circuit monitors the
incoming data stream. If the incoming data stream has no transition for more than 2.5
s, Loss of Signal is
declared. This LOS condition will be cleared when the circuit detects transitions in a 128
s interval sliding
window. Pulling the DLOSDIS pin signal to a high level in hardware mode or setting DLOSDIS bit in host mode
will disable the internal DLOS detection circuit to permit the framer/mapper interface to determine the Loss of
Signal declaration and clearance criteria for specific applications. The external Signal Detect function is
supported by the SDEXT input. An LVCMOS/LVTTL signal comes from the optical module through an output
usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the
manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High." The
SDEXT and POL inputs are Exclusive OR’ed to determine external Loss of Signal (LOS) condition. In the event
that internal DLOS is detected or an external SDEXT input indicates signal absence, the recovered serial data
output will be forced to a logic state "0," and the LOS status register is set whenever the host mode serial
microprocessor interface is active. This acts as a receive data mute upon LOS function to prevent data
chattering and to prevent random noise from being misinterpreted as valid incoming data. Figure 7 shows the
Loss of Signal Detection logic circuit. Table 4 specifies LOS declaration polarity settings.
FIGURE 7. LOSS OF SIGNAL DECLARATION CIRCUIT
TABLE 4: EXTERNAL LOS DECLARATION POLARITY SETTING
SDEXT
POL
INTERNAL SIGNAL DETECT
LOS BIT STATE
(HOST MODE ONLY)
RXDO[3:0]P/N
0
Active Low. Optical signal presence
indicated by SDEXT logic 0 input from
optical module.
Low
Normal
Operation
0
1
Active High. Optical signal presence
indicated by SDEXT logic 1 input from
optical module.
High
LOS declared
Muted
1
0
Active Low. Optical signal presence
indicated by SDEXT logic 0 input from
optical module.
High
LOS declared
Muted
1
Active High. Optical signal presence
indicated by SDEXT logic 1 input from
optical module.
Low
Normal
Operation
DLOSDIS
(Internal) DLOS Detect
(External) SDEXT
LOS Declaration
POL
and
Recovered Data Mute
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L80 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L80_0507 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L80ES | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L80IB | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L80IB-F | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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