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参数资料
| 型号： | 1GBE-PCS-O4-N1 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 10/14页 |
| 文件大小： | 0K |
| 描述： | IP CORE ETH PCS 1GB ORT42G5 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | 1GBEPCSO4N1 |
Lattice Semiconductor
1GbE PCS IP Core User’s Guide
1GbE PCS Core Design Flow
The 1GbE PCS IP Core can be implemented using various methods. The scope of this document covers only the
push-button Graphical User Interface (GUI) ?ow. Figure 2 illustrates the software ?ow model used when evaluating
with the 1GbE PCS.
Figure 2. Lattice IP Core Evaluation Flow
Start
Install and launch ispLEVER software
Obtain desired IP package (download
Core Evaluation package or purchase
IP package)
Protected
Install IP package
Simulation
Model
IP Core Netlist
Perform functional simulation with
the provided core model
Synthesize top-level design with the
IP black box declaration
Place and route the design
Run static timing analysis
Done
Functional Simulation
Simulation script ?les are provided in the “eval” directory for RTL simulation. These scripts rely on the sysbus and
ORT42G5 models already installed with the ispLEVER ? software which includes the ORT42G5 device. If these
models are not installed, they should be installed before proceeding with this IP Core evaluation.
The script ?le <user_compile.do > will compile all of the user code in the evaluation. The user code for this IP core
is the top level chip module. The script ?le <user_vsim.do> will need to be modi?ed by the user to point to the sys-
bus and ORT42G5 simulation models (The ORT42G5 uses the ort82g5_work simulation model). Once modi?ed
this script will load the full chip and testbench. The script ?le <user_wave.do> will add all of the appropriate wave-
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