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参数资料
| 型号： | 1GBE-PCS-O4-N1 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 8/14页 |
| 文件大小： | 0K |
| 描述： | IP CORE ETH PCS 1GB ORT42G5 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | 1GBEPCSO4N1 |
Lattice Semiconductor
Signal Descriptions
Table 4. Signal De?nitions for 1GbE PCS Solution I/O
1GbE PCS IP Core User’s Guide
Line Interface
Signal Name
Clocks and Resets
RX_CLK_125
TX_CLK_125
RST_N
USR_CLK
GMII/MAC Interface
RX_DV
RX_D [7:0]
RX_ER
TX_ER
TX_D [7:0]
TX_DV
MDIO Signals
MDC
MDIO
1
REFCLKN_A
REFCLKP_A
HDINN_AC
HDINP_AC
HDOUTN_AC
HDOUTP_AC
Direction
Input
Input
Input
Input
Output
Output
Output
Input
Input
Input
Input
Input/Output
Input
Input
Input
Input
Output
Output
Description
Receive Clock (125MHz)
Transmit Clock (125MHz)
Active Low Reset
Clock for the User Master Interface
Receive Data Valid
Receive Data Bus
Receive
Transmit Error Indicator
Transmit Data Bus
Transmit Data Valid
MDIO clock
MDIO bi-directional data
CML reference clock input – SERDES Quad A
CML reference clock input – SERDES Quad A
High-speed CML receive data input – SERDES Quad A, Channel C
High-speed CML receive data input – SERDES Quad A, Channel C
High-speed CML receive data output – SERDES Quad A, Channel C
High-speed CML receive data output – SERDES Quad A, Channel C
Auto-negotiation Signals (if MDIO is not implemented)
MR_ADV_ABILITY[15:0]
MR_AN_ENABLE
MR_RESTART_EN
MR_AN_COMPLETE
MR_LP_ADV_ABILITY[15:0]
MR_PAGE_RX
LINK_STATUS
Input
Input
Input
Output
Output
Output
Output
Advertisement Register
Enable Auto-negotiation
Restart Auto-negotiation
Auto-negotiation Complete
Link Partner Ability Register
Page Received
Link Status
Control Signals (if MDIO is not implemented)
MR_MAIN_RESET
MR_LOOPBACK
Input
Input
Core Reset
Enable Loopback
1. The signals listed here are required for the Embedded SPI-4 interface Quad A, Channel C. Please refer to the ORT42G5 Data Sheet for
additional information on con?guring the SPI-4 interface for speci?c applications.
8
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