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参数资料
| 型号： | 1GBE-PCS-O4-N1 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 6/14页 |
| 文件大小： | 0K |
| 描述： | IP CORE ETH PCS 1GB ORT42G5 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | 1GBEPCSO4N1 |
Lattice Semiconductor
Table 3. Register Map for 1GbE PCS Core (Continued)
1GbE PCS IP Core User’s Guide
Address: 0x1
Name: Status Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
ES
R
PS
ANC
RF
ANA
LS
JD
EC
Default value: 0x0109
Description:
ES
R
PS
RF
ANA
LS
JD
EC
ANC
Address: 0x2
Mode: Read Only
Extended Status Information in Register 15. Bit set to One
Reserved. Bit set to zero
Preamble Suppression. Not supported. Bit set to zero
Remote Fault
Auto-negotiation Ability. Bit set to One
Link Status
Jabber Detect. Not supported. Bit set to zero
Extended Register capability
Auto-negotiation Complete
Name: PHY Identi?er Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PHY2
Default value: 0x2222
Description:
PHY2
Address: 0x3
Mode: Read Only
Combined with Register 3 it forms a 32-bit value which serves as an identi?er.
Name: PHY Identi?er Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PHY3
Default value: 0x3333
Description:
PHY3
Address: 0x4
Mode: Read Only
Combined with Register 2 it forms a 32-bit value which serves as an identi?er.
Name: Auto-negotiation Advertisement Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NP
R
RF
RESERVED
PAUSE
HD
FD
RESERVED
Default value: 0x01
Mode: Read/Write
Description: This register contains the Advertised Ability of the PHY.
RESERVED, R
FD
HD
PAUSE
RF
NP
Reserved bits are set to zero
Full Duplex mode supported. Bit set to One
Half Duplex mode not supported. Bit set to Zero
Provides Pause capability exchange mechanism
Remote Fault encoding not supported. Bits set to zero
Next Page Function. Not supported. Bit set to zero.
6
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