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| 型号： | 1GBE-PCS-O4-N1 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 5/14页 |
| 文件大小： | 0K |
| 描述： | IP CORE ETH PCS 1GB ORT42G5 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | 1GBEPCSO4N1 |
Lattice Semiconductor
1GbE PCS IP Core User’s Guide
Register Descriptions
These registers are accessed through the Management Interface (SMI). They are only present if Auto-negotiation
and Management Interface options are selected. The registers are based on the register de?nition in the Section
22 of IEEE 802.3-2002.
Table 2. Top Level Register Addresses
Register Name
Control Register
Status Register
PHY Identi?er Register
PHY Identi?er Register
Auto-negotiation Advertisement Register
Auto-negotiation Link Partner Ability Register
Auto-negotiation Expansion Register
Extended Status Register
Table 3. Register Map for 1GbE PCS Core
Register Address
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0xf
Address: 0x0
Name: Control Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RST
LP
SS0
ANE
PD
IS
RAN
DUP
COL
SS1
RESERVED
Default value: 0x0140
Description:
RST
LP
SS0, SS1
ANE
RAN
PD
IS
COL
DUP
Mode: Read/Write
1 = Reset; 0 = Normal operation. Self clearing
Enables Loopback mode
Speed Selection set to “01” – indicates 1000 Mb/s. Read only
Auto-negotiation Enable
Restart Auto-negotiation. Self clearing
Unsupported functions. Set to Zero. Read only
Unsupported functions. Set to Zero. Read only
Unsupported functions. Set to Zero. Read only
Duplex mode. Set to One – only Full Duplex supported. Read only.
5
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