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参数资料
| 型号： | 1GBE-PCS-O4-N1 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 9/14页 |
| 文件大小： | 0K |
| 描述： | IP CORE ETH PCS 1GB ORT42G5 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | 1GBEPCSO4N1 |
Lattice Semiconductor
1GbE PCS IP Core User’s Guide
Table 5. Signal De?nitions for 1GbE PCS Solution - FPGA/Embedded ASB Interface (Internal to ORT42G5
Device) 1
FPGA
Signal Name
Receive Interface Signals
RSYSCLK_A2
RCK78A
MRWDAC[39]
MRWDAC[38]
MRWDAC[37:30]
MRWDAC[29]
MRWDAC[28]
MRWDAC[27:20]
MRWDAC[19]
MRWDAC[18]
MRWDAC[17:10]
MRWDAC[9]
MRWDAC[8]
MRWDAC[7:0]
Transmit Interface Signals
TSYSCLK_AC
TCK78A
TWDAC[31:0]
TCOMMAAC[3:0]
TBIT9AC[3:0]
Direction
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Output
Output
Output
Description
Low-speed receive FIFO clock for Channel AC
Receive low-speed clock to FPGA – SERDES Quad A
Code violation for Receive Data Byte 3 Channel AC
K_CTRL for Receive Data Byte 3 Channel AC
Receive Data Byte 3 Channel AC
Code violation for Receive Data Byte 2 Channel AC
K_CTRL for Receive Data Byte 2 Channel AC
Receive Data Byte 2 Channel AC
Code violation for Receive Data Byte 1 Channel AC
K_CTRL for Receive Data Byte 1 Channel AC
Receive Data Byte 1 Channel AC
Code violation for Receive Data Byte 0 Channel AC
K_CTRL for Receive Data Byte 0 Channel AC
Receive Data Byte 0 Channel AC
Transmit Low Speed Clock Channel AC
Transmit Low Speed Clock to FPGA – SERDES Quad A
Transmit Data Channel AC
Transmit Comma Character Channel AC
Transmit Force Negative Disparity Channel AC
1. The signals listed here are required for the Embedded SPI-4 interface Quad A, Channel C. Please refer to the ORT42G5 Data Sheet for
additional information on con?guring the SPI-4 interface for speci?c applications.
9
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