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参数资料
| 型号： | 37M602 |
| 厂商： | SMSC Corporation |
| 英文描述： | ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT |
| 中文描述： | 增强的超级I / O控制器，支持红外线 |
| 文件页数： | 3/182页 |
| 文件大小： | 650K |
| 代理商： | 37M602 |
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100
from/to the FIFO does not
cross the threshold.
The interrupt generated is ISA friendly in that it
must pulse the interrupt line low,
allowing for
interrupt sharing.
After a brief pulse low
following the interrupt event, the interrupt line is
tri-stated so that other interrupts may assert.
An interrupt is generated when:
1. For DMA transfers: When serviceIntr is “0”,
dmaEn is “1” and the DMA TC is received.
2. For Programmed I/O:
a.
When serviceIntr is “0”, dmaEn is “0”,
direction
is
“0”
and
there
are
writeIntrThreshold or more free bytes in
the
FIFO.
Also,
an
interrupt
is
generated when serviceIntr is cleared
to
“0”
whenever
there
are
writeIntrThreshold or more free bytes in
the FIFO.
b.(1) When serviceIntr is “0”, dmaEn is “0”,
direction
is
“1”
and
there
are
readIntrThreshold or more bytes in the
FIFO.
Also, an interrupt is generated
when
serviceIntr
is
cleared
to
0
whenever there are readIntrThreshold
or more bytes in the FIFO.
3. When
nErrIntrEn
is
“0”
and
nFault
transitions
from
high
to
low
or
when
nErrIntrEn is set from “1” to “0” and nFault is
asserted.
4. When ackIntEn is “1” and the nAck signal
transitions from a low to a high.
FIFO Operation
The
FIFO
threshold
is
set
in
the
chip
configuration registers. All data transfers to or
from the parallel port can proceed in DMA or
Programmed I/O (non-DMA) mode as indicated
by the selected mode.
The FIFO is used by
selecting the Parallel Port FIFO mode or ECP
Parallel Port Mode. (FIFO test mode will be
addressed separately). After a reset, the FIFO
is disabled. Each data byte is transferred by a
Programmed I/O cycle or PDRQ depending on
the selection of DMA or Programmed I/O mode.
The following paragraphs detail the operation of
the FIFO flow control.
In these descriptions,
<threshold> ranges from 1 to 16. The parameter
FIFOTHR, which the user programs, is one less
and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases.
The host must be very
responsive to the service request.
This is the
desired case for use with a "fast" system.
A
high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in
more frequent service requests.
DMA TRANSFERS
DMA transfers are always to or from the
ecpDFifo, tFifo or CFifo.
DMA utilizes the
standard PC DMA services. To use the DMA
transfers, the host first sets up the direction and
state as in the programmed I/O case. Then it
programs the DMA controller in the host with the
desired count and memory address. Lastly it
sets dmaEn to 1 and serviceIntr to 0. The ECP
requests DMA transfers from the host by
activating the PDRQ pin. The DMA will empty
or fill the FIFO using the appropriate direction
and mode. When the terminal count in the DMA
controller is reached, an interrupt is generated
and serviceIntr is asserted, disabling DMA. In
order to prevent possible blocking of refresh
requests dReq shall not be asserted for more
than 32 DMA cycles in a row.
The FIFO is
enabled directly by asserting nPDACK and
addresses
need
not
be
valid.
PINTR
is
generated when a TC is received. PDRQ must
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