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参数资料
| 型号： | 4430-T-B1 D 950 |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 42/47页 |
| 文件大小： | 799K |
| 描述： | KIT DEV TEST EZRADIOPRO SI4430 |
| 标准包装： | 1 |
| 附件类型： | 测试卡，收发器，950MHz |
| 适用于相关产品： | EZRadioPRO? |
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Si4430/31/32-B1
42
Rev 1.1
The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When the
incoming RX data crosses the Almost Full Threshold an interrupt will be generated to the microcontroller via the
nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.
Both the TX and RX FIFOs may be cleared or reset with the ffclrtx and ffclrrx bits. All interrupts may be enabled by
setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and Register 06h. Interrupt Enable 2. If the
interrupts are not enabled the function will not generate an interrupt on the nIRQ pin but the bits will still be read
correctly in the Interrupt Status registers.
6.2. Packet Configuration
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. "Register 30h.
Data Access Control" through Register 4Bh. Received Packet Length control the configuration, status, and
decoded RX packet data for Packet Handling. The usual fields for network communication (such as preamble,
synchronization word, headers, packet length, and CRC) can be configured to be automatically added to the data
payload. The fields needed for packet generation normally change infrequently and can therefore be stored in
registers. Automatically adding these fields to the data payload greatly reduces the amount of communication
between the microcontroller and the Si4430/31/32 and reduces the required computational power of the
microcontroller.
The general packet structure is shown in Figure 18. The length of each field is shown below the field. The preamble
pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields have programmable
lengths to accommodate different applications. The most common CRC polynominals are available for selection.
Figure 18. Packet Structure
An overview of the packet handler configuration registers is shown in Table 13.
Add R/W Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
08 R/W Operating &
Function
Control 2
antdiv[2] antdiv[1] antdiv[0]
rxmpk
autotx
enldm
ffclrrx
ffclrtx
00h
7C R/W
TX FIFO
Control 1
Reserved Reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0]
37h
7D R/W
TX FIFO
Control 2
Reserved Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0]
04h
Add R/W Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
7E R/W
RX FIFO
Control
Reserved Reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0]
37h
Data
Preamble
CRC
1-255 Bytes
1-4 Bytes
0 or 2
Bytes
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