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参数资料
| 型号： | 5962-9561501MLX |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 8-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CDIP24 |
| 封装： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件页数： | 18/22页 |
| 文件大小： | 203K |
| 代理商： | 5962-9561501MLX |
REV. B
AD7890
–5–
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Description
1
AGND
Analog Ground. Ground reference for track/hold, comparator and DAC.
2
SMODE
Control Input. Determines whether the part operates in its External Clocking (slave) or Self-Clocking
(master) serial mode. With SMODE at a logic low, the part is in its Self-Clocking serial mode with
RFS and SCLK as outputs. This Self-Clocking mode is useful for connection to shift registers or to
serial ports of DSP processors. With SMODE at a logic high, the part is in its External Clocking
serial mode with SCLK and
RFS as inputs. This External Clocking mode is useful for connection to
the serial port of microcontrollers such as the 8xC51 and the 68HCxx and for connection to the
serial ports of DSP processors.
3
DGND
Digital Ground. Ground reference for digital circuitry.
4CEXT
External Capacitor. An external capacitor is connected to this pin to determine the length of the
internal pulse (see
CONVST input and Control Register section). Larger capacitances on this pin
extend the pulse to allow for settling time delays through an external antialiasing filter or signal
conditioning circuitry.
5
CONVST
Convert Start. Edge-triggered logic input. A low to high transition on this input puts the track/hold
into hold and initiates conversion provided that the internal pulse has timed out (see Control
Register section). If the internal pulse is active when the
CONVST goes high, the track/hold will not
go into hold until the pulse times out. If the internal pulse has timed out when
CONVST goes high,
the rising edge of
CONVST drives the track/hold into hold and initiates conversion.
6
CLK IN
Clock Input. An external TTL-compatible clock is applied to this input pin to provide the clock source
for the conversion sequence. In the Self-Clocking serial mode, the SCLK output is derived from this
CLK IN pin.
7
SCLK
Serial Clock Input. In the External Clocking (slave) mode (see Serial Interface section) this is an
externally applied serial clock which is used to load serial data to the control register and to access
data from the output register. In the Self-Clocking (master) mode, the internal serial clock, which is
derived from the clock input (CLK IN), appears on this pin. Once again, it is used to load serial data
to the control register and to access data from the output register.
8
TFS
Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the
falling edge of this signal.
9
RFS
Receive Frame Synchronization Pulse. In the External Clocking mode, this pin is an active low logic
input with
RFS provided externally as a strobe or framing pulse to access serial data from the output
register. In the Self-Clocking mode, it is an active low output which is internally generated
and provides a strobe or framing pulse for serial data from the output register. For applications
which require that data be transmitted and received at the same time,
RFS and TFS should be
connected together.
10
DATA OUT
Serial Data Output. Sixteen bits of serial data are provided with one leading zero, preceding the three
address bits of the Control register and the 12 bits of conversion data. Serial data is valid on the
falling edge of SCLK for sixteen edges after
RFS goes low. Output coding from the ADC is two’s
complement for the AD7890-10 and straight binary for the AD7890-4 and AD7890-2.
11
DATA IN
Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first
five bits of serial data are loaded to the control register on the first five falling edges of SCLK after
TFS goes low. Serial data on subsequent SCLK edges is ignored while TFS remains low.
12
VDD
Positive supply voltage, 5 V
± 5%.
13
MUX OUT
Multiplexer Output. The output of the multiplexer appears at this pin. The output voltage range
from this output is 0 V to 2.5 V for the nominal analog input range to the selected channel. The
output impedance of this output is nominally 3.5 k
. If no external antialiasing filter is required,
MUX OUT should be connected to SHA IN.
14
SHA IN
Track/Hold Input. The input to the on-chip track/hold is applied to this pin. It is a high impedance
input and the input voltage range is 0 V to 2.5 V.
15
AGND
Analog Ground. Ground reference for track/hold, comparator and DAC.
16
VIN1
Analog Input Channel 1. Single-ended analog input. The analog input range on is
±10 V (AD7890-10),
0 V to 4.096 V (AD7890-4) and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected
using the A0, A1 and A2 bits in the control register. The multiplexer has guaranteed break-before-
make operation.
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