参数资料
型号: 5962R9684502VXA
元件分类: SRAM
英文描述: 4K X 9 DUAL-PORT SRAM, 45 ns, PGA68
封装: PGA-68
文件页数: 15/21页
文件大小: 496K
代理商: 5962R9684502VXA
3
Figure 2b: DPRAM Pinout (68 PGA)
(top view)
Notes:
1. I/O8R on the7C139
2. I/O8L on the 7C139
PIN NAMES
B11
A5L
C11
A4L
D11
A2L
E11
A0L
F11
BUSYL
G11
M/S
H11
NC
J11
A1R
K11
A3R
A10
A7L
B10
A6L
C10
A3L
D10
A1L
E10
NC
F10
GND
G10
BUSYR
H10
A0R
J10
A2R
K10
A4R
L10
A5R
A9
A9L
B9
A8L
K9
A7R
L9
A6R
A8
A11L
B8
A10L
K8
A9R
L8
A8R
A7
VDD
B7
NC
K7
A11R
L7
A10R
A6
NC
B6
NC
K6
GND
L6
NC
A5
NC
B5
CEL
K5
NC
L5
NC
A4
OEL
B4
R/WL
K4
NC
L4
CER
A3
I/O0L
B3
NC
(2)
K3
OER
L3
R/WR
A2
I/O1L
B2
I/O2L
C2
I/O4L
D2
GND
E2
I/O7L
F2
GND
G2
I/O1R
H2
VDD
J2
I/O4R
K2
I/O7R
L2
NC
(1)
B1
I/O3L
C1
I/O5L
D1
I/O6L
E1
VDD
F1
I/O0R
G1
I/O2R
H1
I/O3R
J1
I/O5R
K1
I/O6R
LEFT PORT
RIGHT PORT
DESCRIPTION
I/O0L-7L(8L)
I/O0R-7R(8R)
Data Bus Input/Output
A0L-11L
A0R-11R
Address Lines
CEL
CER
Chip Enable
OEL
OER
Output Enable
R/WL
R/WR
Read/Write Enable
BUSYL
BUSYR
Busy Flag Input/Output
M/S
Master or Slave Select
VDD
Power
GND
Ground
7C138/139
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
H
J
K
L
G
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