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参数资料
| 型号： | 5962R9684502VXA |
| 元件分类： | SRAM |
| 英文描述： | 4K X 9 DUAL-PORT SRAM, 45 ns, PGA68 |
| 封装： | PGA-68 |
| 文件页数： | 3/21页 |
| 文件大小： | 496K |
| 代理商： | 5962R9684502VXA |
11
Address
CE
R/ W
Data in
tWC
tSCE
t
AW
tPWE
tSA
t
SD
DATA VALID
t
HA
t
LZWE
tHD
tHZWE
HIGH IMPEDANCE
Figure 4b. Write Cycle 2: R/W Three-States Data I/Os (Either Port)
Assumptions:
1. The internal write time of memory is defined by the overlap of CE
LOW and R/ W LOW. Both signals must be LOW to initialize a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the sig-
nal that terminates the write.
2. R/W must be HIGH during all address transactions.
3. Data I/O pins enter high impedance even if OE is held LOW during
write.
Data out
tWHWL
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