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参数资料
| 型号： | 5962R9684502VXA |
| 元件分类： | SRAM |
| 英文描述： | 4K X 9 DUAL-PORT SRAM, 45 ns, PGA68 |
| 封装： | PGA-68 |
| 文件页数： | 2/21页 |
| 文件大小： | 496K |
| 代理商： | 5962R9684502VXA |
10
Address
CE
R/ W
Data in
OE
Data out
tWC
tSCE
tAW
tPWE
t
HA
tSA
tSD
tHZOE
t
LZOE
DATA VALID
HIGH IMPE DANCE
tHD
Assumptions:
1. The internal write time of memory is defined by the overlap of CE
LOW and R/W LOW. Both signals must be LOW to initiate a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the
signal that terminates the write.
2. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tPWE or (tHZWE + tSD ) to allow the I/O
drivers to turn off and data to be placed on the bus for the required t SD.
If OE is HIGH during a R/W controlled write cycle (as in this exam-
ple), this requirement does not apply and the write pulse can be as
short as the specified tPWE.
3. R/W must be HIGH during all address transactions.
Figure 4a. Write Cycle 1: OE Three-States Data I/Os (Either Port)
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