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参数资料
| 型号： | 5962R9684502VXA |
| 元件分类： | SRAM |
| 英文描述： | 4K X 9 DUAL-PORT SRAM, 45 ns, PGA68 |
| 封装： | PGA-68 |
| 文件页数： | 6/21页 |
| 文件大小： | 496K |
| 代理商： | 5962R9684502VXA |
14
AddressL,R
CEL
CER
BUSY
R
AddressL,R
CER
CEL
BUSY
L
ADDRESS MATCH
tPS
t
BLC
tBZC
tPS
tBLC
t
BZC
Figure 5c. BUSY Timing Diagram No. 1 (CE Arbitration)
CE
L Valid First:
CE R Valid First:
Assumptions:
1. If tPS is violated, the BUSY signal will be asserted on
one side or the other, but there is no guarantee on which
side BUSY will be asserted.
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