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参数资料
| 型号： | 5962R9684502VXA |
| 元件分类： | SRAM |
| 英文描述： | 4K X 9 DUAL-PORT SRAM, 45 ns, PGA68 |
| 封装： | PGA-68 |
| 文件页数： | 21/21页 |
| 文件大小： | 496K |
| 代理商： | 5962R9684502VXA |
9
AC CHARACTERISTICS WRITE CYCLE 1
(VDD = 5.0V±10%)
Notes:
1. For information on part-to-part delay through DPRAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform (see figure 3c).
SYMBOL
PARAMETER
7C138 - 45
7C139 - 45
MIN
MAX
7C138 - 55
7C139 - 55
MIN
MAX
UNIT
tWC
Write cycle time
45
55
ns
t
SCE
CE LOW to write end
40
50
ns
tAW
Address set-up to write end
40
50
ns
tHA
Address hold from write end
0
ns
tSA
Address set-up to write start
0
ns
t
PWE
Write pulse width
40
50
ns
tSD
Data set-up to write end
40
50
ns
tHD
Data hold from write end
0
ns
tHZWE
R/W LOW to high Z
20
ns
t
LZWE
R/W HIGH to low Z
0
ns
tWDD
Write pulse to data delay
95
105
ns
tDDD
Write data valid to read data valid
95
105
ns
tWHWL
Write disable time
5
ns
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