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参数资料
| 型号： | 72225LB25TFG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 1K X 18 OTHER FIFO, 15 ns, PQFP64 |
| 封装： | GREEN, PLASTIC, STQFP-64 |
| 文件页数： | 12/16页 |
| 文件大小： | 178K |
| 代理商： | 72225LB25TFG |
5
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OCTOBER 22, 2008
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)
Commercial
Commercial & Industrial(1)
IDT72205LB10
IDT72205LB15
IDT72205LB25
IDT72215LB10
IDT72215LB15
IDT72215LB25
IDT72225LB10
IDT72225LB15
IDT72225LB25
IDT72235LB10
IDT72235LB15
IDT72235LB25
IDT72245LB10
IDT72245LB15
IDT72245LB25
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
—
100
—
66.7
—
40
MHz
tA
Data Access Time
2
6.5
2
10
2
15
ns
tCLK
Clock Cycle Time
10
—
15
—
25
—
ns
tCLKH
Clock HIGH Time
4.5
—
6
—
10
—
ns
tCLKL
Clock LOW Time
4.5
—
6
—
10
—
ns
tDS
DataSet-upTime
3
—
4
—
6
—
ns
tDH
Data Hold Time
0
—
1
—
1
—
ns
tENS
EnableSet-upTime
3
—
4
—
6
—
ns
tENH
Enable Hold Time
0
—
1
—
1
—
ns
tRS
Reset Pulse Width(2)
10
—
15
—
25
—
ns
tRSS
ResetSet-upTime
8
—
10
—
15
—
ns
tRSR
Reset Recovery Time
8
—
10
—
15
—
ns
tRSF
Reset to Flag and Output Time
—
15
—
20
—
25
ns
tOLZ
Output Enable to Output in Low-Z(3)
0—
ns
tOE
Output Enable to Output Valid
3
6
3
8
3
12
ns
tOHZ
Output Enable to Output in High-Z(3)
36
38
3
12
ns
tWFF
Write Clock to Full Flag
—
6.5
—
10
—
15
ns
tREF
Read Clock to Empty Flag
—
6.5
—
10
—
15
ns
tPAF
Clock to Asynchronous Programmable Almost-Full Flag
—
17
—
24
—
26
ns
tPAE
Clock to Programmable Almost-Empty Flag
—
17
—
24
—
26
ns
tHF
Clock to Half-Full Flag
—
17
—
24
—
26
ns
tXO
Clock to Expansion Out
—
6.5
—
10
—
15
ns
tXI
Expansion In Pulse Width
3
—
6.5
—
10
—
ns
tXIS
Expansion In Set-Up Time
3.5
—
5
—
10
—
ns
tSKEW1
Skew time between Read Clock & Write Clock forFull Flag
5
—
6
—
10
—
ns
tSKEW2(2)
Skew time between Read Clock & Write Clock for
Empty Flag
5—
6—
10
—
ns
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
OutputReferenceLevels
1.5V
OutputLoad
See Figure 1
AC TEST CONDITIONS
Figure 1. Output Load
* Includes jig and scope capacitances.
30pF*
1.1K
5V
680
D.U.T.
2766 drw 04
NOTES:
1. Industrial temperature range product for the 15ns and the 25ns speed grades are available as a standard device. All other speed grades are available by special order.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
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