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参数资料
| 型号： | 72225LB25TFG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 1K X 18 OTHER FIFO, 15 ns, PQFP64 |
| 封装： | GREEN, PLASTIC, STQFP-64 |
| 文件页数： | 13/16页 |
| 文件大小： | 178K |
| 代理商： | 72225LB25TFG |
6
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OCTOBER 22, 2008
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
CONTROLS:
RESET (
RS)
ResetisaccomplishedwhenevertheReset(
RS)inputistakentoaLOWstate.
During reset, both internal read and write pointers are set to the first location.
A reset is required after power-up before a write operation can take place. The
Full Flag (
FF),Half-FullFlag(HF)andProgrammableAlmost-FullFlag(PAF)
will be reset to HIGH after tRSF. The Empty Flag (
EF) and Programmable
Almost-EmptyFlag(
PAE)willberesettoLOWaftertRSF. Duringreset,theoutput
registerisinitializedtoallzerosandtheoffsetregistersareinitializedtotheirdefault
values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH
transitionofWCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (
WEN)
When the
WENinput isLOWandLDinputisHIGH,datamaybeloadedinto
the FIFO RAM array on the rising edge of every WCLK cycle if the device is
not full. Data is stored in the RAM array sequentially and independently of any
ongoing read operation.
When
WENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
Topreventdataoverflow,
FFwillgoLOW,inhibitingfurtherwriteoperations.
Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to
occur. The
FF flag is updated on the rising edge of WCLK. WEN is ignored
when the FIFO is full.
READ CLOCK (RCLK)
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock (RCLK), when Output Enable (
OE) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (
REN)
When Read Enable is LOW and
LD input is HIGH, data is loaded from the
RAM array into the output register on the rising edge of every RCLK cycle if
the device is not empty.
Whenthe
RENinputisHIGH,theoutputregisterholdsthepreviousdataand
nonewdataisloadedintotheoutputregister. ThedataoutputsQ0-Qnmaintain
the previous data value.
Every word accessed at Qn, including the first word written to an empty
FIFO, must be requested using
REN. Whenthelastwordhasbeenreadfrom
the FIFO, the Empty Flag (
EF)willgoLOW,inhibitingfurtherreadoperations.
REN is ignored when the FIFO is empty. Once a write is performed, EF will
go HIGH allowing a read to occur. The
EF flag is updated on the rising edge
of RCLK.
OUTPUT ENABLE (
OE)
When Output Enable (
OE) is enabled (LOW), the parallel output buffers
receivedatafromtheoutputregister.When
OEisdisabled(HIGH),theQoutput
data bus is in a high-impedance state.
LOAD (
LD)
The IDT72205LB/72215LB/72225LB/72235LB/72245LB devices con-
tain two 12-bit offset registers with data on the inputs, or read on the outputs.
When the Load (
LD) pin is set LOW and WEN is set LOW, data on the inputs
D0-D11 is written into the Empty Offset register on the first LOW-to-HIGH
transition of the Write Clock (WCLK). When the
LD pin and (WEN) are held
LOWthendataiswrittenintotheFullOffsetregisteronthesecondLOW-to-HIGH
transitionof(WCLK).Thethirdtransitionofthewriteclock(WCLK)againwrites
totheEmptyOffsetregister.
However,writingalloffsetregistersdoesnothavetooccuratonetime.One
or two offset registers can be written and then by bringing the
LDpinHIGH,the
FIFO is returned to normal read/write operation. When the
LD pinissetLOW,
and
WEN is LOW, the next offset register in sequence is written.
EMPTY OFFSET REGISTER
17
11
0
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
FULL OFFSET REGISTER
17
11
0
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
2766 drw 05
Figure 2. Write Offset Register
NOTE:
1. The same selection sequence applies to reading from the registers.
REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
Figure 3. Offset Register Location and Default Values
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
LD
WEN
WCLK
Selection
0
Writingtooffsetregisters:
Empty Offset
FullOffset
0
1
No Operation
1
0
Write Into FIFO
1
No Operation
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