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参数资料
| 型号： | 72225LB25TFG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 1K X 18 OTHER FIFO, 15 ns, PQFP64 |
| 封装： | GREEN, PLASTIC, STQFP-64 |
| 文件页数： | 15/16页 |
| 文件大小： | 178K |
| 代理商： | 72225LB25TFG |
8
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OCTOBER 22, 2008
Afterhalfofthememoryisfilled,andattheLOW-to-HIGHtransitionofthenext
write cycle, the Half-Full Flag goes LOW and will remain set until the difference
between the write pointer and read pointer is less than or equal to one half of
the total memory of the device. The Half-Full Flag (
HF) is then reset to HIGH
by the LOW-to-HIGH transition of the Read Clock (RCLK). The
HF is
asynchronous.
In the Daisy Chain Depth Expansion mode,
WXI is connected to WXO of
the previous device. This output acts as a signal to the next device in the Daisy
Chain by providing a pulse when the previous device writes to the last location
of memory.
READ EXPANSION OUT (
RXO)
In the Daisy Chain Depth Expansion configuration, Read Expansion In
(
RXI)isconnectedtoReadExpansionOut(RXO)ofthepreviousdevice.This
outputactsasasignaltothenextdeviceintheDaisyChainbyprovidingapulse
when the previous device reads from the last location of memory.
DATA OUTPUTS (Q0-Q17)
Q0-Q17 are data outputs for 18-bit wide data.
,
t
RSF
RS
RSR
Q0 - Q17
t RSF
= 0
= 1
(1)
2766 drw 06
tRSS
NOTES:
1. After reset, the outputs will be LOW if
OE = 0 and tri-state if OE = 1.
2. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing(2)
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相关代理商/技术参数 |
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| 72225LB25TFI | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 18 64-Pin STQFP 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 1KX18 64TQFP - Rail/Tube |
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