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参数资料
| 型号： | 72V285L15TFI9 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 64K X 18 OTHER FIFO, 10 ns, PQFP64 |
| 封装： | STQFP-64 |
| 文件页数： | 10/25页 |
| 文件大小： | 266K |
| 代理商： | 72V285L15TFI9 |
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
Figure
10.
Read
Timing
(First
Word
Fall
Through
Mode
)
NOTES:
1.
t
SKEW1
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
IR
will
go
LOW
after
one
WCLK
cycle
plus
t
WFF
.
If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
than
t
SKEW1
,then
the
IR
assertion
may
be
delayed
one
extra
WCLK
cycle.
2.
tSKEW2
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
PAF
will
go
HIGH
after
one
WCLK
cycle
plus
t
PAF
.
If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
than
t
SKEW2
,then
the
PAF
deassertion
may
be
delayed
one
extra
WCLK
cycle.
3.
LD
=
HIGH
4
.
n=
PAE
Offset,
m
=
PAF
offset
and
D
=
maximum
FIFO
depth.
5
.
D
=
32,769
for
IDT72V275
and
65,537
for
IDT72V285.
WCLK
12
WEN
D
0
-
D
17
RCLK
tENS
REN
Q
0
-Q
17
PAF
HF
PAE
IR
OR
W
1
W
1
W
2
W
3
W
m+2
W
[m+3]
tOHZ
tSKEW1
tENH
tDS
tDH
tOE
tA
tPAF
tWFF
tENS
OE
tSKEW2
W
D
4512
drw
13
tPAE
W
[D-n]
W
[D-n-1]
tA
tHF
tREF
W
[D-1]
W
D
tA
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
tENS
D-1
]
[
W
D-1
]
[
W
1
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相关代理商/技术参数 |
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| 72V285L20PF | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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| 72V291L10PF | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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