参数资料
型号: 72V285L15TFI9
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: FIFO
英文描述: 64K X 18 OTHER FIFO, 10 ns, PQFP64
封装: STQFP-64
文件页数: 25/25页
文件大小: 266K
代理商: 72V285L15TFI9
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
Figure 4. Programmable Flag Offset Programming Sequence
Figure 3. Offset Register Location and Default Values
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
WCLK
RCLK
X
XX
X
XX
4512 drw 07
LD
0
X
1
0
WEN
0
1
0
X
1
REN
1
0
1
X
0
1
X
SEN
1
X
0
72V275
72V285
Parallel write to registers:
Empty Offset
Full Offset
Parallel read from registers:
Empty Offset
Full Offset
No Operation
Write Memory
Read Memory
No Operation
Serial shift into registers:
30 bits for the 72V275
32 bits for the 72V285
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
EMPTY OFFSET REGISTER
17
0
007FH if
LD is LOW at Master Reset,
03FFH if
LD is HIGH at Master Reset
FULL OFFSET REGISTER
17
0
DEFAULT VALUE
007FH if
LD is LOW at Master Reset,
03FFH if
LD is HIGH at Master Reset
14
72V275 (32,768 x 18_BIT)
15
14
15
EMPTY OFFSET REGISTER
17
0
007FH if
LD is LOW at Master Reset,
03FFH if
LD is HIGH at Master Reset
FULL OFFSET REGISTER
17
0
DEFAULT VALUE
007FH if
LD is LOW at Master Reset,
03FFH if
LD is HIGH at Master Reset
15
72V285 (65,536 x 18_BIT)
4512 drw 06
16
15
16
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