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参数资料
| 型号： | 72V285L15TFI9 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 64K X 18 OTHER FIFO, 10 ns, PQFP64 |
| 封装： | STQFP-64 |
| 文件页数： | 19/25页 |
| 文件大小： | 266K |
| 代理商： | 72V285L15TFI9 |
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
DESCRIPTION (Continued)
Figure 1. Block Diagram of Single 32,768 x 18 and 65,536 x 18 Synchronous FIFO
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
MASTER RESET (
MRS)
READ CLOCK (RCLK)
READ ENABLE (
REN)
OUTPUT ENABLE (
OE)
EMPTY FLAG/OUTPUT READY (
EF/OR)
PROGRAMMABLE ALMOST-EMPTY (
PAE)
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN)
LOAD (
LD)
FULL FLAG/INPUT READY (
FF/IR)
PROGRAMMABLE ALMOST-FULL (
PAF)
IDT
72V275
72V285
PARTIAL RESET (
PRS)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (
RT)
4512 drw 03
HALF-FULL FLAG (
HF)
SERIAL ENABLE(
SEN)
These FIFOs have five flag pins,
EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF(Half-full Flag), PAE (Programmable
Almost-Empty flag) and
PAF(ProgrammableAlmost-Fullflag). TheEFand
FF functions are selected in IDT Standard mode. TheIR and OR functions
are selected in FWFT mode.
HF, PAE and PAF are always available for
use, irrespective of timing mode.
PAE andPAF canbeprogrammedindependentlytoswitchatanypoint
in memory. (See Table 1 and Table 2.) Programmable offsets determine the
flag switching threshold and can be loaded by two methods: parallel or serial.
Two default offset settings are also provided, so that
PAEcanbesettoswitch
at 127 or 1,023 locations from the empty boundary and the
PAFthresholdcan
besetat127or1,023locationsfromthefullboundary. Thesechoicesaremade
with the
LD pin during Master Reset.
For serial programming,
SEN together with LD on each rising edge of
WCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,
WENtogetherwithLDoneachrisingedgeofWCLK,areused
to load the offset registers via Dn.
RENtogetherwithLDoneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serial or parallel offset loading has been selected.
DuringMasterReset(
MRS)thefollowingeventsoccur:Thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The
LDpinselectseitherapartialflagdefault
setting of 127 with parallel programming or a partial flag default setting of 1,023
with serial programming. The flags are updated according to the timing mode
anddefaultoffsetsselected.
The Partial Reset (
PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag programming
method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect.
PRS is useful for resetting a device in mid-operation, when
reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the
RTinputduringarisingRCLKedgeinitiatesaretransmit
operation by setting the read pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT72V275/72V285 are fabricated using IDT’s high speed submicron
CMOS technology.
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相关代理商/技术参数 |
参数描述 |
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| 72V285L20PF | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72V285L20PF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18 64-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 64KX18 64TQFP - Tape and Reel |
| 72V285L20TF | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72V285L20TF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 64KX18 64TQFP - Tape and Reel |
| 72V291L10PF | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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