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| 型号： | 935271490512 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封装： | PLASTIC, MS-018, SOT-188-2, LCC-68 |
| 文件页数： | 17/56页 |
| 文件大小： | 715K |
| 代理商： | 935271490512 |
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Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
24 of 53
9397 750 11002
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive
FIFO trigger levels, and select the DMA mode.
7.3.1
DMA mode
Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C454 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever an empty transmit space is available in the Transmit Holding
Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The
transmit interrupt is set when there are one or more FIFO locations empty. The
receive interrupt is set when the receive FIFO lls to the programmed trigger level.
However, the FIFO continues to ll regardless of the programmed level until the FIFO
is full. RXRDY remains a logic 0 as long as the FIFO ll level is above the
programmed trigger level.
7.3.2
FIFO mode
Table 10:
FIFO Control Register bits description
Bit
Symbol
Description
7-6
FCR[7]
(MSB),
FCR[6]
(LSB)
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
Logic 0 (or cleared) = normal default condition.
Logic 1 = RX trigger level = 8.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to Table 11.
5-4
FCR[5-4]
Not used; initialized to logic 0.
3
FCR[3]
DMA mode select.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C554/554D is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are
no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the rst character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C554/554D is in
mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1;
FCR[3] = logic 0) and there is at least one character in the receive FIFO,
the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a
logic 1 when there are no more characters in the receiver.
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