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参数资料
| 型号： | 935271490512 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封装： | PLASTIC, MS-018, SOT-188-2, LCC-68 |
| 文件页数： | 2/56页 |
| 文件大小： | 715K |
| 代理商： | 935271490512 |
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Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
10 of 53
9397 750 11002
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
D0-D2,
D3-D7
66-68,
1-5
53-55,
56-60
7-9,
11-15
I/O
Data bus (bi-directional). These pins are the 8-bit, 3-State data bus
for transferring information to or from the controlling CPU. D0 is the
least signicant bit and the rst data bit in a transmit or receive serial
data stream.
DSRA,
DSRB,
DSRC, DSRD
10, 26,
44, 60
1, 17,
32, 48
22, 39,
62, 79
I
Data Set Ready (Active-LOW). These inputs are associated with
individual UART channels, A through D. A logic 0 on this pin indicates
the modem or data set is powered-on and is ready for data exchange
with the UART. This pin has no effect on the UART’s transmit or
receive operation.
DTRA,
DTRB,
DTRC, DTRD
12, 24,
46, 58
3, 15,
34, 46
24, 37,
64, 77
O
Data Terminal Ready (Active-LOW). These outputs are associated
with individual UART channels, A through D. A logic 0 on this pin
indicates that the SC16C554/554D is powered-on and ready. This pin
can be controlled via the modem control register. Writing a logic 1 to
MCR[0] will set the DTR output to logic 0, enabling the modem. This
pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
This pin has no effect on the UART’s transmit or receive operation.
GND
6, 23,
40, 57
14, 28,
45, 61
16, 36,
56, 76
I
Signal and power ground.
INTA, INTB,
INTC, INTD
15, 21,
49, 55
6, 12,
37, 43
27, 34,
67, 74
O
Interrupt A, B, C, D (Active-HIGH). This function is associated with
the 16 mode only. These pins provide individual channel interrupts
INTA-INTD. INTA-INTD are enabled when MCR[3] is set to a logic 1,
interrupts are enabled in the interrupt enable register (IER), and
when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty,
or when a modem status ag is detected. When the 68 mode is
selected, the functions of these pins are re-assigned. 68 mode
functions are described under their respective name/pin headings.
INTSEL
65
-
6
I
Interrupt Select (Active-HIGH, with internal pull-down). This
function is associated with the 16 mode only. When the 16 mode is
selected, this pin can be used in conjunction with MCR[3] to enable
or disable the 3-State interrupts, INTA-INTD, or override MCR[3] and
force continuous interrupts. Interrupt outputs are enabled
continuously by making this pin a logic 1. Making this pin a logic 0
allows MCR[3] to control the 3-State interrupt output. In this mode,
MCR[3] is set to a logic 1 to enable the 3-State outputs. This pin is
disabled in the 68 mode. Due to pin limitations on the 64-pin
packages, this pin is not available. To cover this limitation, the
SC16C654DIB64 version operates in the continuous interrupt enable
mode by bonding this pin to VCC internally. The ST16C654IB64
operates with MCR[3] control by bonding this pin to GND.
IOR
52
40
70
I
Input/Output Read strobe (Active-LOW). This function is
associated with the 16 mode only. A logic 0 transition on this pin will
load the contents of an internal register dened by address bits
A0-A2 onto the SC16C554/554D data bus (D0-D7) for access by
external CPU. This pin is disabled in the 68 mode.
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
PLCC68 LQFP64 LQFP80
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