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参数资料
| 型号： | 935271490512 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封装： | PLASTIC, MS-018, SOT-188-2, LCC-68 |
| 文件页数： | 5/56页 |
| 文件大小： | 715K |
| 代理商： | 935271490512 |
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Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
13 of 53
9397 750 11002
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.
Functional description
The SC16C554/554D provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character. Data integrity is insured by attaching a parity bit to the
data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex,
especially when manufactured on a single integrated silicon chip. The
SC16C554/554D represents such an integration with greatly enhanced features. The
SC16C554/554D is fabricated with an advanced CMOS process to achieve low drain
power and high speed requirements.
The SC16C554/554D is an upward solution that provides 16 bytes of transmit and
receive FIFO memory, instead of none in the 16C454. The SC16C554/554D is
designed to work with high speed modems and shared network environments that
require fast data processing time. Increased performance is realized in the
SC16C554/554D by the larger transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a given time. In addition, the four
selectable levels of FIFO trigger interrupt and automatic hardware/software ow
control is uniquely provided for maximum data throughput performance, especially
when operating in a multi-channel environment. The combination of the above greatly
reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The SC16C554/554D combines the package interface modes of the 16C454/554 and
68C454/554 series on a single integrated chip. The 16 mode interface is designed to
operate with the Intel-type of microprocessor bus, while the 68 mode is intended to
operate with Motorola and other popular microprocessors. Following a reset, the
SC16C554/554D is downward compatible with the 16C454/554 or the 68C454/554,
dependent on the state of the interface mode selection pin, 16/68.
The SC16C554/554D is capable of operation to 1.5 Mbits/s with a 24 MHz crystal
and up to 5 Mbits/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the
maximum speed is 3 Mbits/s).
The rich feature set of the SC16C554/554D is available through internal registers.
Automatic hardware/software ow control, selectable transmit and receive FIFO
trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface,
modem interface controls, and a sleep mode are all standard features. MCR[5]
provides a facility for turning off (Xon) software ow control with any incoming (RX)
character. In the 16 mode, INTSEL and MCR[3] can be congured to provide a
software controlled or continuous interrupt capability. Due to pin limitations of the
64-pin package, this feature is offered by two different LQFP64 packages. The
SC16C554D operates in the continuous interrupt enable mode by bonding INTSEL to
VCC internally. The SC16C554 operates in conjunction with MCR[3] by bonding
INTSEL to GND internally.
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