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参数资料
| 型号： | 9UMS9633BKLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 166.67 MHz, OTHER CLOCK GENERATOR, PQCC48 |
| 封装： | 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MLF-48 |
| 文件页数： | 12/22页 |
| 文件大小： | 208K |
| 代理商： | 9UMS9633BKLFT |
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1423—01/20/09
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
2
Advance Information
SSOP Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
REF
OUT
14.318 MHz reference clock.
2
GNDREF
PWR Ground pin for the REF outputs.
3
VDDCORE_3.3
PWR 3.3V power for the PLL core
4FSC_L
IN
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
5TEST_MODE
IN
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
6
TEST_SEL
IN
TEST_SEL: latched input to select TEST MODE
1 = All outputs are tri-stated for test
0 = All outputs behave normally.
7
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
8
SDATA
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
9
VDDCORE_3.3
PWR 3.3V power for the PLL core
10
VDDIO_1.5
PWR Power supply for low power differential outputs, nominal 1.5V.
11
DOT96C_LPR
OUT
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
12
DOT96T_LPR
OUT
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
13
GNDDOT
PWR Ground pin for DOT clock output
14
GNDLCD
PWR Ground pin for LCD clock output
15
LCD100C_LPR
OUT
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
16
LCD100T_LPR
OUT
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
17
VDDIO_1.5
PWR Power supply for low power differential outputs, nominal 1.5V.
18
VDDCORE_3.3
PWR 3.3V power for the PLL core
19
*CR#0
IN
Clock request for SRC0, 0 = enable, 1 = disable
20
GNDSRC
PWR Ground pin for the SRC outputs
21
SRCC0_LPR
OUT
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
22
SRCT0_LPR
OUT
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
23
*CR#1
IN
Clock request for SRC1, 0 = enable, 1 = disable
24
VDDCORE_3.3
PWR 3.3V power for the PLL core
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