参数资料
型号: 9UMS9633BKLFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 166.67 MHz, OTHER CLOCK GENERATOR, PQCC48
封装: 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MLF-48
文件页数: 6/22页
文件大小: 208K
代理商: 9UMS9633BKLFT
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1423—01/20/09
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
14
Advance Information
Byte
2
Output Enable Register
Bit(s)
Pin #
Name
Description
Type
0
1
Default
7
CPU0 Enable
This bit controls whether the CPU[0] output buffer
is enabled or not.
RW
0 = Disabled
1 = Enabled
1
6
CPU1 Enable
This bit controls whether the CPU[1] output buffer
is enabled or not.
RW
0 = Disabled
1 = Enabled
1
5
CPU2 Enable
This bit controls whether the CPU[2] output buffer
is enabled or not.
RW
0 = Disabled
1 = Enabled
1
4
SRC0 Enable
This bit controls whether the SRC[0] output buffer
is enabled or not.
RW
0 = Disabled
1 = Enabled
1
3
SRC1 Enable
This bit controls whether the SRC[1] output buffer
is enabled or not.
RW
0 = Disabled
1 = Enabled
1
2
SRC2 Enable
This bit controls whether the SRC[2] output buffer
is enabled or not.
RW
0 = Disabled
1 = Enabled
1
DOT Enable
This bit controls whether the DOT output buffer is
enabled or not.
RW
0 = Disabled
1 = Enabled
1
0
LCD100 Enable
This bit controls whether the LCD output buffer is
enabled or not.
RW
0 = Disabled
1 = Enabled
1
Byte
3
Output Control Register
Bit(s)
Pin #
Name
Description
Type
0
1
Default
7
0
6
0
5
REF Enable
This bit controls whether the REF output buffer is
enabled or not.
RW
0 = Disabled
1 = Enabled
1
4
3
2
CPU0 Stop Enable
This bit controls whether the CPU[0] output buffer
is free-running or stoppable. If it is set to stoppable
the CPU[0] output buffer will be disabled with the
assertion of CPU_STP#.
RW
Free Running
Stoppable
0
1
CPU1 Stop Enable
This bit controls whether the CPU[1] output buffer
is free-running or stoppable. If it is set to stoppable
the CPU[1] output buffer will be disabled with the
assertion of CPU_STP#.
RW
Free Running
Stoppable
0
CPU2 Stop Enable
This bit controls whether the CPU[2] output buffer
is free-running or stoppable. If it is set to stoppable
the CPU[2] output buffer will be disabled with the
assertion of CPU_STP#.
RW
Free Running
Stoppable
0
10
REF Slew
00 = Slow Edge Rate
01 = Medium Edge Rate
10 = Fast Edge Rate
11 = Reserved
RW
These bits control the edge rate of the REF clock.
Reserved
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