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参数资料
| 型号： | 9UMS9633BKLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 166.67 MHz, OTHER CLOCK GENERATOR, PQCC48 |
| 封装： | 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MLF-48 |
| 文件页数： | 16/22页 |
| 文件大小： | 208K |
| 代理商： | 9UMS9633BKLFT |
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1423—01/20/09
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
3
Advance Information
SSOP Pin Description (continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
25
VDDIO_1.5
PWR Power supply for low power differential outputs, nominal 1.5V.
26
SRCC1_LPR
OUT
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
27
SRCT1_LPR
OUT
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
28
GNDSRC
PWR Ground pin for the SRC outputs
29
SRCC2_LPR
OUT
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
30
SRCT2_LPR
OUT
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
31
*CR#2
IN
Clock request for SRC2, 0 = enable, 1 = disable
32
FSB_L
IN
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
33
CPUC2_LPR
OUT
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
34
CPUT2_LPR
OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
35
GNDCPU
PWR Ground pin for the CPU outputs
36
VDDIO_1.5
PWR Power supply for low power differential outputs, nominal 1.5V.
37
VDDCORE_3.3
PWR 3.3V power for the PLL core
38
CPUC1_LPR
OUT
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
39
CPUT1_LPR
OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
40
GNDCPU
PWR Ground pin for the CPU outputs
41
VDDIO_1.5
PWR Power supply for low power differential outputs, nominal 1.5V.
42
CPUC0_LPR
OUT
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
43
CPUT0_LPR
OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
44
CPU_STOP#
IN
Stops all CPU clocks, except those set to be free running clocks
45
CLKPWRGD#/PD_3.3
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / Asynchronous
active high input pin used to place the device into a power down state.
46
X2
OUT
Crystal output, Nominally 14.318MHz
47
X1
IN
Crystal input, Nominally 14.318MHz.
48
VDDREF_3.3
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
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