参数资料
型号: A28F400BX-B
英文描述: 4-MBIT (256K x16. 512K x8) BOOT BLOCK FLASH MEMORY FAMILY
中文描述: 4兆位(256K x16。为512k × 8)启动块闪存系列
文件页数: 32/36页
文件大小: 457K
代理商: A28F400BX-B
A28F400BR-T/B
E
32
ADVANCE INFORMATION
Table 14. AC Characteristics: CE#
–Controlled Write Operations
(1,12)
Symbol
Parameter
Notes
Min
Max
Unit
t
AVAV
t
PHEL
t
WLEL
t
PHHEH
t
VPEH
t
AVEH
t
DVEH
t
ELEH
t
EHDX
t
EHAX
t
EHWH
t
EHEL
t
EHQV1
Write Cycle Time
80
ns
RP# High Recovery to CE# Going Low
450
ns
WE# Setup to CE# Going Low
0
ns
Boot Block Lock Setup to CE# Going High
6,8
100
ns
V
PP
Setup to CE# Going High
Address Setup to CE# Going High
5,8
100
ns
60
ns
Data Setup to CE# Going High
3
60
ns
CE# Pulse Width
4
60
ns
Data Hold Time from CE# High
0
ns
Address Hold Time from CE# High
4
10
ns
WE# Hold Time from CE# High
3
10
ns
CE# Pulse Width High
20
ns
Duration of Word/Byte Program Operation
2,5
7
μs
t
EHQV2
Duration of Erase Operation (Boot)
2,5,6
0.4
s
t
EHQV3
Duration of Erase Operation (Parameter)
2,5
0.4
s
t
EHQV4
Duration of Erase Operation (Main)
2,5
0.7
s
t
QWL
t
QVPH
t
PHBR
NOTES:
See WE# Controlled Write Operations for notes 1 through 11.
12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE#
defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be
measured relative to the CE# waveform.
V
PP
Hold from Valid SRD
RP# V
HH
Hold from Valid SRD
Boot-Block Relock Delay
5,8
0
ns
6,8
0
ns
7,8
100
ns
相关PDF资料
PDF描述
A28F400BR-TB Toggle Switch; Circuitry:DPDT; Switch Operation:On-On; Contact Current Max:6A; Actuator Style:Bat; Switch Terminals:Through Hole; Current Rating:3A; Leaded Process Compatible:Yes; Mounting Type:PCB; Features:Standard Actuator RoHS Compliant: Yes
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