参数资料
型号: A28F400BX-B
英文描述: 4-MBIT (256K x16. 512K x8) BOOT BLOCK FLASH MEMORY FAMILY
中文描述: 4兆位(256K x16。为512k × 8)启动块闪存系列
文件页数: 8/36页
文件大小: 457K
代理商: A28F400BX-B
A28F400BR-T/B
E
8
ADVANCE INFORMATION
1.5
Pin Descriptions
Table 1. 28F400 Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
17
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally
latched during a write cycle.
A
9
INPUT
ADDRESS INPUT:
When A
9
is at V
HH
the signature mode is accessed.
During this mode, A
0
decodes between the manufacturer and device IDs.
When BYTE# is at a logic low, only the lower byte of the signatures are
read. DQ
15
/A
-1
is a don’t care in the signature mode when BYTE# is low.
DQ
0
–DQ
7
INPUT/OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched during the Write cycle. Outputs array, Intelligent
Identifier and Status Register data. The data pins float to tri-state when
the chip is de-selected or the outputs are disabled.
DQ
8
–DQ
15
INPUT/OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched during
the Write cycle. Outputs array data. The data pins float to tri-state when
the chip is de-selected or the outputs are disabled as in the byte-wide
mode (BYTE# = “0”). In the byte-wide mode DQ
15
/A–
1
becomes the
lowest order address for data output on DQ
0
–DQ
7
.
CE#
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels. If
CE# and RP# are high, but not at a CMOS high level, the standby current
will increase due to current flow through the CE# and RP# input stages.
OE#
INPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data buffers
during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the Command Register and array
blocks. WE# is active low. Addresses and data are latched on the rising
edge of the WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN:
Uses three voltage levels (V
IL
, V
IH
, and
V
HH
) to control two different functions: reset/deep power-down mode and
boot block unlocking. It is backwards-compatible with the 28F400BX/BL.
When RP# is at logic low, the device is in reset/deep power-down
mode
, which puts the outputs at High-Z, resets the Write State Machine,
and draws minimum current.
When RP# is at logic high, the device is in standard operation
. When
RP# transitions from logic-low to logic-high, the device defaults to the
read array mode.
When RP# is at V
HH
, the boot block is unlocked
and can be
programmed or erased. This overrides any control from the WP# input.
相关PDF资料
PDF描述
A28F400BR-TB Toggle Switch; Circuitry:DPDT; Switch Operation:On-On; Contact Current Max:6A; Actuator Style:Bat; Switch Terminals:Through Hole; Current Rating:3A; Leaded Process Compatible:Yes; Mounting Type:PCB; Features:Standard Actuator RoHS Compliant: Yes
A28F400BX-T 4-MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY
A29-1 10 TO 1500 MHz CASCADABLE AMPLIFIER
A290011SERIES 128K X 8 Bit CMOS 5.0 Volt-only. Boot Sector Flash Memory
A29001SERIES 128K X 8 Bit CMOS 5.0 Volt-only. Boot Sector Flash Memory
相关代理商/技术参数
参数描述
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