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| 型号： | A3941KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 16/21页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET FULL BRDG AUTO 28TSSOP |
| 标准包装： | 1 |
| 配置： | 半桥 |
| 输入类型： | PWM |
| 延迟时间： | 90ns |
| 配置数： | 1 |
| 输出数： | 4 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 产品目录页面： | 1140 (CN2011-ZH PDF) |
| 其它名称： | 620-1236-6 |
A3941
Automotive Full Bridge MOSFET Driver
t CHARGE = , (6)
voltage of the Zener diodes between the Cx and Sx pins. In most
applications, with a good ceramic capacitor the working voltage
can be limited to 16 V.
Bootstrap Charging
It is good practice to ensure the high-side bootstrap capacitor is
completely charged before a high-side PWM cycle is requested.
The time required to charge the capacitor, t CHARGE ( μ s), is
approximated by:
C BOOT × ? V
100
where C BOOT is the value of the bootstrap capacitor, in nF, and
? V is the required voltage of the bootstrap capacitor.
At power-up and when the drives have been disabled for a long
time, the bootstrap capacitor can be completely discharged. In
this case ? V can be considered to be the full high-side drive
voltage, 12 V. Otherwise, ? V is the amount of voltage dropped
during the charge transfer, which should be 400 mV or less.
The capacitor is charged whenever the Sx pin is pulled low and
current flows from VREG through the internal bootstrap diode
circuit to C BOOT .
Bootstrap Charge Management
The A3941 provides automatic bootstrap capacitor charge
management. The bootstrap capacitor voltage for each phase
is continuously checked to ensure that it is above the bootstrap
under-voltage threshold, V BOOTUV . If the bootstrap capacitor volt-
age drops below this threshold, the A3941 will turn on the neces-
sary low-side FET, and continue charging until the bootstrap
capacitor exceeds the undervoltage threshold plus the hysteresis,
V BOOTUV + V BOOTUVhys . The minimum charge time is typically
7 μ s, but may be longer for very large values of bootstrap capaci-
tor (>1000 nF). If the bootstrap capacitor voltage does not reach
the threshold within approximately 200 μ s, an undervoltage fault
will be flagged.
capacitors. When a low-side FET is turned on, the gate-drive
circuit will provide the high transient current to the gate that is
necessary to turn on the FET quickly. This current, which can be
several hundred milliamperes, cannot be provided directly by the
limited output of the VREG regulator, and must be supplied by an
external capacitor connected to VREG.
The turn-on current for the high-side FET is similar in value to
that for the low-side FET, but is mainly supplied by the boot-
strap capacitor. However the bootstrap capacitor must then be
recharged from the VREG regulator output. Unfortunately the
bootstrap recharge can occur a very short time after the low-
side turn-on occurs. This requires that the value of the capacitor
connected between VREG and AGND should be high enough to
minimize the transient voltage drop on VREG for the combina-
tion of a low-side FET turn-on and a bootstrap capacitor recharge.
A value of 20 × C BOOT is a reasonable value. The maximum
working voltage will never exceed V REG , so the capacitor can be
rated as low as 15 V. This capacitor should be placed as close as
possible to the VREG pin.
Supply Decoupling
Because this is a switching circuit, there are current spikes from all
supplies at the switching points. As with all such circuits, the power
supply connections should be decoupled with a ceramic capacitor,
typically 100 nF, between the supply pin and ground. These capaci-
tors should be connected as close as possible to the device supply
pins VBB and V5, and the ground pin, GND.
Power Dissipation
In applications where a high ambient temperature is expected, the
on-chip power dissipation may become a critical factor. Careful
attention should be paid to ensure the operating conditions allow
the A3941 to remain in a safe range of junction temperature.
The power consumed by the A3941, P D , can be estimated by:
VREG Capacitor Selection
P D = P BIAS + P CPUMP + P SWITCHING ,
(7)
The internal reference, VREG, supplies current for the low-side
gate drive circuits and the charging current for the bootstrap
given:
P BIAS = V BB × I BB ;
Allegro MicroSystems, LLC
115 Northeast Cutoff
(8)
16
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A3942 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Quad High-Side Gate Driver |
| A3942KLG-T | 制造商:Allegro MicroSystems LLC 功能描述:IC,Quad MOSFET Driver,TSSOP,38PIN,PLASTIC |
| A3942KLGTR-T | 功能描述:IC GATE DVR QUAD HISIDE 38-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:5 系列:- 配置:低端 输入类型:非反相 延迟时间:600ns 电流 - 峰:12A 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:- 电源电压:14.2 V ~ 15.8 V 工作温度:-20°C ~ 60°C 安装类型:通孔 封装/外壳:21-SIP 模块 供应商设备封装:模块 包装:散装 配用:BG2A-NF-ND - KIT DEV BOARD FOR IGBT 其它名称:835-1063 |
| A39438-000 | 制造商:TE Connectivity 功能描述:3012-11-230510-CS2324 |
| A3944 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Automotive, Low-Side FET Pre-Driver |
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