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| 型号： | A3941KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 8/21页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET FULL BRDG AUTO 28TSSOP |
| 标准包装： | 1 |
| 配置： | 半桥 |
| 输入类型： | PWM |
| 延迟时间： | 90ns |
| 配置数： | 1 |
| 输出数： | 4 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 产品目录页面： | 1140 (CN2011-ZH PDF) |
| 其它名称： | 620-1236-6 |
A3941
Automotive Full Bridge MOSFET Driver
In some applications a safety resistor is added between the gate
and source of each FET in the bridge. When a high-side FET is
held in the on-state, the current through the associated high-side
gate-source resistor (R GSH ) is provided by the high-side drive and
therefore appears as a static resistive load on the top-off charge
pump. The minimum value of R GSH for which the top-off charge
pump can provide current is shown in the Electrical Characteris-
tics table.
GLA and GLB Pins These are the low-side gate drive outputs for
the external N-channel MOSFETs. External resistors between the
gate drive output and the gate connection to the FET (as close as
possible to the FET) can be used to control the slew rate seen at
the gate, thereby providing some control of the di/dt and dv/dt of
the SA and SB outputs. GLx going high turns on the upper half of
the drive, sourcing current to the gate of the low-side FET in the
external power bridge, turning it on. GLx going low turns on the
lower half of the drive, sinking current from the external FET gate
circuit to the LSS pin, turning off the FET.
SA and SB Pins Directly connected to the motor, these terminals
sense the voltages switched across the load. These terminals are
also connected to the negative side of the bootstrap capacitors
and are the negative supply connections for the floating high-side
drives. The discharge current from the high-side FET gate capaci-
tance flows through these connections, which should have low
impedance circuit connections to the FET bridge.
GHA and GHB Pins These terminals are the high-side gate
drive outputs for the external N-channel FETs. External resistors
between the gate drive output and the gate connection to the FET
(as close as possible to the FET) can be used to control the slew
rate seen at the gate, thereby controlling the di/dt and dv/dt of the
SA and SB outputs. GHx going high turns on the upper half of
the drive, sourcing current to the gate of the high-side FET in the
external motor-driving bridge, turning it on. GHx going low turns
on the lower half of the drive, sinking current from the external
FET gate circuit to the corresponding Sx pin, turning off the FET.
CA and CB Pins These are the high-side connections for the
bootstrap capacitors and are the positive supply for the high-side
gate drives. The bootstrap capacitors are charged to approxi-
mately V REG when the associated output Sx terminal is low.
When the Sx output swings high, the charge on the bootstrap
capacitor causes the voltage at the corresponding Cx terminal to
rise with the output to provide the boosted gate voltage needed
for the high-side FETs.
LSS Pin This is the low-side return path for discharge of the
capacitance on the FET gates. It should be tied directly to the
common sources of the low-side external FETs through an inde-
pendent low impedance connection.
RDEAD Pin This pin controls internal generation of dead time
during FET switching.
? When a resistor greater than 3 k Ω is connected between
RDEAD and AGND, cross-conduction is prevented by the gate
drive circuits, which introduce a dead time, t DEAD , between
switching one FET off and the complementary FET on. The
dead time is derived from the resistor value connected between
the RDEAD and AGND pins.
? When RDEAD is connected directly to V5, cross-conduction is
prevented by the gate drive circuits. In this case, t DEAD defaults
to a value of 6 μ s typical.
Logic Control Inputs
Four low-voltage level digital inputs provide control for the
gate drives. These logic inputs all have a nominal hysteresis of
500 mV to improve noise performance. They are used together
to provide fast decay or slow decay with high-side or low-side
recirculation. They also provide brake, coast, and sleep modes as
defined in tables 1 and 2.
PWMH and PWML Pins These inputs can be used to control
current in the power bridge. PWMH provides high-side chopping
and PWML provides low-side chopping. When used together
they control the power bridge in fast decay mode. The PWM
options are provided in table 2.
? Setting PWMH low turns off active high-side drives. This
provides high-side–chopped slow-decay PWM.
? Setting PWML low turns off active low-side drives. This
provides low-side–chopped slow-decay PWM.
? PWMH and PWML may also be connected together and driven
with a single PWM signal. This provides fast-decay PWM.
PHASE Pin The state of the PHASE pin determines the positive
direction of load current (see table 1). The PHASE pin can also
be used as a PWM input when full four-quadrant control (fast
decay synchronous rectification) is required (see table 2).
SR Pin This enables or disables synchronous rectification. When
SR is high, synchronous rectification is enabled. When a PWM-
off phase occurs (low on either or both of the PWMH and PWML
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A3942 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Quad High-Side Gate Driver |
| A3942KLG-T | 制造商:Allegro MicroSystems LLC 功能描述:IC,Quad MOSFET Driver,TSSOP,38PIN,PLASTIC |
| A3942KLGTR-T | 功能描述:IC GATE DVR QUAD HISIDE 38-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:5 系列:- 配置:低端 输入类型:非反相 延迟时间:600ns 电流 - 峰:12A 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:- 电源电压:14.2 V ~ 15.8 V 工作温度:-20°C ~ 60°C 安装类型:通孔 封装/外壳:21-SIP 模块 供应商设备封装:模块 包装:散装 配用:BG2A-NF-ND - KIT DEV BOARD FOR IGBT 其它名称:835-1063 |
| A39438-000 | 制造商:TE Connectivity 功能描述:3012-11-230510-CS2324 |
| A3944 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Automotive, Low-Side FET Pre-Driver |
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