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参数资料
| 型号： | A3992SLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 10/13页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRVR PWM DUAL 24-TSSOP |
| 标准包装： | 1 |
| 应用： | PWM 电机驱动器，步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±1.5A |
| 电压 - 负载： | 15 V ~ 50 V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | 620-1170-6 |
A3992
Layout . The printed circuit board should use a heavy
groundplane. For optimum electrical and thermal
performance, the A3992 must be soldered directly
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
under the device, to serve both as a low impedance
ground point and thermal path.
The two input capacitors should be placed in parallel,
onto the board. On the underside of the A3992 pack-
age is an exposed pad, which provides a path for
enhanced thermal dissipation. The thermal pad should
be soldered directly to an exposed surface on the PCB.
Thermal vias are used to transfer heat to other layers
of the PCB.
In order to minimize the effects of ground bounce and
offset issues, it is important to have a low impedance
single-point ground, known as a star ground, located
very close to the device. By making the connection be-
tween the pad and the ground plane directly under the
A3992, that area becomes an ideal location for a star
ground point. A low impedance ground will prevent
ground bounce during high current operation and en-
sure that the supply voltage remains stable at the input
terminal. The recommended PCB layout, shown in the
diagram below, illustrates how to create a star ground
and as close to the device supply pins as possible. The
ceramic capacitor (CVBB1) should be closer to the
pins than the bulk capacitor (CVBB2). This is neces-
sary because the ceramic capacitor will be responsible
for delivering the high frequency current components.
The sense resistors, RSx , should have a very low
impedance path to ground, because they must carry
a large current while supporting very accurate volt-
age measurements by the current sense comparators.
Long ground traces will cause additional voltage
drops, adversely affecting the ability of the compara-
tors to accurately measure the current in the wind-
ings. As shown in the layout below, the SENSEx pins
have very short traces to the RSx resistors and very
thick, low impedance traces directly to the star ground
underneath the device.
OUT1A
OUT1B
OUT1A
OUT1B
V BB
GND
VBB
1
SENSE1
VBB1
CS1
RS1
U1
CS1
RS1
OUT1A
NC
STROBE
A3992
NC
OUT1B
CP2
CCP
CCP
CVCP
CLOCK
DATA
PAD
CP1
VCP
CVCP
CREF
CREF
GND
REF
MUX
VDD
GND
OSC
SLEEP
VREG
ROSC
CREG
CVBB2
CVDD
RS2
ROSC
CREG
CVBB2
CVBB1
CS2
RS2
OUT2A
SENSE2
OUT2B
VBB2
CVBB1
CS2
VREF
OUT2A
OUT2B
VREF
OUT2A
CVDD
OUT2B
LP package layout shown
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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