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参数资料
| 型号： | A3992SLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 8/13页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRVR PWM DUAL 24-TSSOP |
| 标准包装： | 1 |
| 应用： | PWM 电机驱动器，步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±1.5A |
| 电压 - 负载： | 15 V ~ 50 V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | 620-1170-6 |
A3992
Charge Pump (CP1 and CP2). The charge pump is
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
Short to Ground. Should a motor winding short to
used to generate a gate supply greater than V BB x to
drive the source FET gates. A 0.22 μ F ceramic capaci-
tor is required between CP1 and CP2 for pumping
purposes. A 0.22 μ F ceramic capacitor is required
between VCP and the VBB terminals to act as a reser-
voir to operate the high-side FETs.
Sleep Mode. Control input on the SLEEP pin is used
to minimize power consumption when not the device
is not in use. This disables much of the internal circuit-
ry including the output DMOS, regulator, and charge
pump. Logic low puts the device into Sleep mode,
logic high allows normal operation and startup of the
device into the home position. When asserted low,
the serial port is reset. All bits are reset to 0s, with the
exception of D7, the ? xed off-time MSB, which is set
to 1. This prevents the off-time from being too short,
which could result in a loss of current control. When
coming out of Sleep mode, allow 1 ms before issuing
a step command, to allow the charge pump to stabilize.
Shutdown. In the event of a fault due to excessive
junction temperature, or to low voltage on V CP or
V REG , the outputs of the device are disabled until the
fault condition is removed. At power up, and in the
event of low V DD , the UVLO circuit disables the driv-
ers and resets the data in the serial port.
Fault latched
2 A / div.
500 ns / div.
(A) Short-to-ground event
ground, the current through the short will rise until the
overcurrent (OCP) threshold is exceeded, a minimum
of 2 A. The driver will turn off after a short propaga-
tion delay and latch the device. The device will remain
latched until the SLEEP input goes high or VDD
power is removed. As shown in panel A of the ? gure
below, a short to ground will produce a single overcur-
rent event.
Shorted Load. During a shorted load event, the cur-
rent path is through the sense resistor. The device will
be protected, however, the device does not see this as a
fault because the current path is not interrupted, so this
condition will not latch the part.
When a bridge turns on, the current will rise and ex-
ceed the overcurrent threshold. After a blank time of
approximately 1 μ s, the driver will look at the voltage
on the SENSE pin. The voltage on the SENSE pin will
be larger than the voltage set by the VREF pin, and
the bridge will turn off for the time set by the OSC
pin. Panel B of the ? gure below shows a shorted load
condition with an off-time of 30 μ s.
MUX. The MUX pin is reserved for Allegro internal
use and has no function to the end user. In the applica-
tion, this pin can be tied to ground or left ? oating.
t off = 30 μ s
2 A / div.
5 μ s / div.
(B) Short-to-load event
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
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