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参数资料
| 型号： | A3992SLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 11/13页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRVR PWM DUAL 24-TSSOP |
| 标准包装： | 1 |
| 应用： | PWM 电机驱动器，步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±1.5A |
| 电压 - 负载： | 15 V ~ 50 V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | 620-1170-6 |
A3992
B Package
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
Device Pin-out Diagrams
LP Package
VCP 1
CP1 2
CP2 3
OUT1B 4
VBB1 5
24 OSC
23 SLEEP
22 VREG
21 OUT2B
20 VBB2
SENSE1 1
OUT1A 2
NC 3
STROBE 4
CLOCK 5
24 VBB1
23 NC
22 OUT1B
21 CP2
20 CP1
GND 6
GND 7
SENSE1 8
OUT1A 9
STROBE 10
CLOCK 11
DATA 12
19 GND
18 GND
17 SENSE2
16 OUT2A
15 VDD
14 MUX
13 REF
DATA 6
GND 7
REF 8
MUX 9
VDD 10
OUT2A 11
SENSE2 12
PAD
19 VCP
18 GND
17 OSC
16 SLEEP
15 VREG
14 OUT2B
13 VBB2
Terminal List Table
Number
B
LP
Name
Pin Description
Package Package
1
2
3
4
5
6, 7, 18, 19
8
9
10
11
12
13
14
15
16
17
20
21
22
23
24
–
–
19
20
21
22
24
7, 18
1
2
4
5
6
8
9
10
11
12
13
14
15
16
17
3, 23
–
VCP
CP1
CP2
OUT1B
VBB1
GND
SENSE1
OUT1A
STROBE
CLOCK
DATA
REF
MUX
VDD
OUT2A
SENSE2
VBB2
OUT2B
VREG
SLEEP
OSC
NC
PAD
Reservoir capacitor terminal
Charge pump capacitor terminal
Charge pump capacitor terminal
DMOS Full Bridge 1, output B
Load supply
Ground. On B package, internally fused to the die pad
for enhanced thermal dissipation.
Sense resistor terminal for Full Bridge 1
DMOS Full Bridge 1, output A
Logic input
Logic input
Logic input
G m reference input
Not used
Logic supply
DMOS Full Bridge 2, output A
Sense resistor terminal for Full Bridge 2
Load supply
DMOS Full Bridge 2, output B
Internal regulator
Logic input
Oscillator input
No connection
Exposed thermal pad for enhanced thermal dissipation.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
11
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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