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| 型号： | A3992SLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 4/13页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRVR PWM DUAL 24-TSSOP |
| 标准包装： | 1 |
| 应用： | PWM 电机驱动器，步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±1.5A |
| 电压 - 负载： | 15 V ~ 50 V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | 620-1170-6 |
A3992
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
ELECTRICAL CHARACTERISTICS 1 valid at T A = 25°C, V BB = 50 V, f PWM < 50 kHz, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. 2
Output Drivers
Max. Units
Load Supply Voltage Range V BB
Operating, I OUT = ±1.5 A 15 – 50 V
During Sleep mode 0 – 50 V
Output Leakage Current I DSS
Output On Resistance R DS(on)
V OUT = V BB – <1.0 50
V OUT = 0 V – <–1.0 –50
Source driver, I OUT = -1.5 A – 0.54 0.6
Sink driver, I OUT = 1.5 A – 0.54 0.6
μ A
μ A
Ω
Ω
Body Diode Forward Voltage V F
Motor Supply Current I BB
Source diode, I F = -1.5 A – – 1.2 V
Sink diode, I F = 1.5 A – – 1.2 V
f PWM < 50 kHz – – 8 mA
Operating, outputs disabled – – 6 mA
Sleep or Idle mode – – 20
μ A
f PWM < 50 kHz – – 12 mA
Logic Supply Current I DD
Outputs off – – 10 mA
Idle mode (Word 1, D18 = 0) – – 1.5 mA
Control Logic
Sleep mode – – 100
μ A
Logic Supply Voltage Range V DD
Operating 4.5 5 5.5 V
Logic Input Voltage
V IN(1)
V IN(0)
2.0 – – V
– – 0.8 V
Logic Input Current
I IN(1)
I IN(0)
V IN = 2.0 V – <1.0 20
V IN = 0.8 V – <–2.0 –20
μ A
μ A
Input Hysteresis
0.20 – 0.40 V
Minimum sleep pulse width t S
>2 – –
μ s
OSC input frequency f OSC(in)
OSC input duty cycle
Internal Oscillator f OSC
DAC Accuracy V DAC
Reference Input Voltage Range
Reference Buffer Offset V OS
Reference Divider Ratio V REF /V SENSE
Divide by 1 (Word 2, D13=0, D14=1) 2.5 – 6 MHz
40 – 60 %
OSC shorted to GND 3 4 5 MHz
R OSC = 51 k Ω 3.4 4 4.6 MHz
Measured relative to REF buffer output – ±0.5 – LSB
.5 – 2.6 V
– ±10 – mV
Word 0, D18 = 0, D17 = 1, V REF = 0.5 to 2.6 V 7.4 8 8.8 –
Word 0, D18 = 1, D17 = 1, V REF =0.5 to 2.6 V 3.6 4 4.4 –
Reference Input Current I REF
V REF = 2.0 V –0.5 – 0.5
μ A
Internal Reference Voltage V REFINT
Comparator Input Offset Volt. V IO
1.940 2.0 2.060 V
V REF = 0 V –5 0 5 mV
Internal V REF , Range = 8, DAC = 63 –6 0 6 %
G M Error
3
V ERR
Internal V REF , Range = 8, DAC = 31 –9 0 9 %
Internal V REF , Range = 4, DAC = 63 –6 0 6 %
Internal V REF , Range = 4, DAC = 15 –10 0 10 %
50% to 90%; PWM change to source on 500 800 1000 ns
Propagation Delay Times tpd
Crossover Dead Time t DT
UVLO Enable Threshold V UVLO
UVLO Hysteresis V UVLOHYS
Protection Circuitry
50% to 90%; PWM change to source off 35 – 250 ns
50% to 90%; PWM change to sink on 500 800 1000 ns
50% to 90%; PWM change to sink off 35 – 250 ns
300 650 900 ns
V DD rising 3.9 4.2 4.45 V
0.05 0.10 – V
Overcurrent Protection Threshold 4
I OCPST
2 – – A
Overcurrent Blanking t OCP
1 – 3
μ s
Thermal Shutdown Temperature T J
Thermal Shutdown Hysteresis T JHYS
– 165 – °C
– 15 – °C
1 Negative current is de ? ned as coming out of (sourcing) the speci ? ed device pin.
2 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the speci ? ed maximum and minimum limits.
3 V ERR = [(V REF / Range) – V SENSE ] / (V REF / Range).
4 OCP is tested at T A = 25°C in a restricted range and guaranteed by characterization.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
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