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参数资料
| 型号： | A3992SLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 7/13页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRVR PWM DUAL 24-TSSOP |
| 标准包装： | 1 |
| 应用： | PWM 电机驱动器，步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±1.5A |
| 电压 - 负载： | 15 V ~ 50 V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | 620-1170-6 |
A3992
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
D14 – D15 Synchronous Recti ? cation. 2 bits set the
different modes of operation (see Synchronous Recti ? -
cation in the Functional Description section):
D16, D17 (Reserved). 2 bits reserved for testing.
They should be programmed to 0 during normal op-
eration.
D15
0
0
1
1
D14
0
1
0
1
Synchronous Rectifier
Active
Disabled
Passive
Allegro defined use
D18 Idle Mode. The device can be put into the low-
power Idle mode by writing a 0 to D18. The outputs
are disabled, the charge pump turned off, and the de-
vice consumes a lower supply current. The undervolt-
age monitor circuit remains active.
Functional Description
VREG. The VREG pin should be decoupled with a
0.22 ? F capacitor to ground. This internally gener-
ated supply voltage is used to run the sink side DMOS
outputs. VREG is internally monitored and in the
case of a fault condition, the outputs of the device are
disabled.
Current Regulation. The reference voltage can be set
by analog input to the REF terminal, or via the internal
2 V precision reference. The choice of reference volt-
age and selection of sense resistor set maximum trip
current, as follows:
I TRIPMAX = V REF / (Range × R SENSE ) .
Microstepping current levels are set according to the
following equations:
I TRIP = V DAC / (Range × R SENSE ) , and
V DAC = ((1+DAC) × V REF ) / 64 ,
where DAC is the input code, 1 to 63 (Word 0, D1 to
D12), and Range is 4 or 8, as selected by Word 0, D18.
Programming a DAC input code to 0 disables the cor-
responding bridge, and results in minimum load current.
PWM Timer Function. The PWM timer is program-
mable via the serial port to provide ? xed off-time
PWM signals to the control block. In mixed decay
mode, the ? rst portion of the off-time operates in fast
decay, until the fast decay time count is reached, fol-
lowed by slow decay for the remainder of the ? xed
off-time. If the fast decay time is set longer than the off-
time, the device effectively operates in fast decay mode.
Oscillator. The PWM timer is based on an oscillator
input, typically 4 MHz. The A3992 can be con ? gured
to select either the 4 MHz internal oscillator or, if
more precise accuracy is required, an external clock
can be connected to the OSC terminal. If an external
clock is used, 3 internal divider choices are selectable
via the serial port to allow ? exibility in choosing f OSC
based on available system clocks. If the internal oscil-
lator option is used, the absolute accuracy is dependent
on process variation of resistance and capacitance.
A precision resistor can be connected from the OSC
terminal to V DD to further improve the tolerance. The
frequency is calculated as:
f OSC = 204 × 10 9 / R OSC .
If the internal oscillator is used without the external re-
sistor the OSC terminal should be connected to GND.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
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