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参数资料
| 型号： | A3992SLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 6/13页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRVR PWM DUAL 24-TSSOP |
| 标准包装： | 1 |
| 应用： | PWM 电机驱动器，步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±1.5A |
| 电压 - 负载： | 15 V ~ 50 V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | 620-1170-6 |
A3992
Word 1 Bit Assignments
Word 1 is selected by setting D0 = 1. Assignments are
summarized in the following table, and described in
detail in the remainder of this section.
Word 1 Bit Assignments
DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
from erroneously resetting the source enable latch,
the sense comparator is blanked. The blank timer runs
after the off time counter to provide the programmable
blanking function. The blank timer is reset when
PHASE is changed.
Bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
Function
Word Select = 1
Blank Time LSB
Blank Time MSB
Off Time LSB
Off Time Bit1
Off Time Bit2
Off Time Bit3
Off Time MSB
Fast Decay Time LSB
Fast Decay Time Bit1
Fast Decay Time Bit2
Fast Decay Time MSB
C0 Oscillator Control
C1 Oscillator Control
SR Control Bit 1
SR Control Bit 2
Reserved for testing
Reserved for testing
Idle Mode
D3 – D7 Fixed Off Time. 5 bits to set the ? xed
off-time for the internal PWM control circuitry. Fixed
off-time is de ? ned by:
t OFF = (1 + n ) × P OSC × 8 – P OSC ,
where n = 0 to 31.
For example, with a master oscillator frequency of
4 MHz ( P OSC = 250 ns), the ? xed off-time is adjust-
able from 1.75 to 63.75 μ s, in increments of 2 μ s.
D8 – D11 Fast Decay Time. 4 bits to set the fast
decay portion of ? xed off-time for the internal PWM
control circuitry. The fast decay portion is de ? ned by:
t fd = (1 + n ) × P OSC × 8 – P OSC ,
where n = 0 to 15.
For example, with a master oscillator frequency of
4 MHz ( P OSC = 250 ns), the ? xed off-time is adjust-
able from 1.75 to 31.75 μ s, in increments of 2 μ s. For
t fd > t off , the device will effectively operate in fast
decay mode.
D12 – D13 Oscillator Control. 2 bits to set timing
D1 – D2 Blank Time. 2 bits to set the blank time scal-
ing factor for the current sense comparator:
options:
D13
0
D12
0
Source and Rate
Internal clock 4 MHz
D2
0
0
D1
0
1
Time
4 × P OSC
6 × P OSC
0
1
1
1
0
1
External clock f ÷ 1
External clock f ÷ 2
External clock f ÷ 4
1
0
8 × P OSC
1
1
12 × P OSC
A 4 MHz internal oscillator can be used for the tim-
ing functions. If more precise control is required, an
When a source driver turns on, a current spike occurs
due to the reverse recovery currents of the clamp di-
odes and/or switching transients related to distributed
capacitance in the load. To prevent this current spike
external oscillator can be input to OSC pin. To accom-
modate a wider range of system clocks, an internal
divider is provided to generate the desired MO fre-
quency.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
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