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参数资料
| 型号： | A3PN250-Z1VQG100I |
| 厂商： | Microsemi SoC |
| 文件页数： | 93/114页 |
| 文件大小： | 0K |
| 描述： | IC FPGA NANO 250K GATES 100-VQFP |
| 标准包装： | 90 |
| 系列： | ProASIC3 nano |
| RAM 位总计： | 36864 |
| 输入/输出数： | 68 |
| 门数： | 250000 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-VQFP（14x14） |
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ProASIC3 nano Device Overview
1-2
Revision 11
Security, built into the FPGA fabric, is an inherent component of ProASIC3 nano devices. The flash cells
are located beneath seven metal layers, and many device design and layout techniques have been used
to make invasive attacks extremely difficult. ProASIC3 nano devices, with FlashLock and AES security,
are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is
protected with industry-standard security, making remote ISP possible. A ProASIC3 nano device
provides the best available security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 nano
FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load
device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and
system reliability.
Instant On
Microsemi flash-based ProASIC3 nano devices support Level 0 of the Instant On classification standard.
This feature helps in system component initialization, execution of critical tasks before the processor
wakes up, setup and configuration of memory blocks, clock generation, and bus activity management.
The Instant On feature of flash-based ProASIC3 nano devices greatly simplifies total system design and
reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used
for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the
ProASIC3 nano device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to
be reloaded when system power is restored. This enables the reduction or complete removal of the
configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from
the PCB design. Flash-based ProASIC3 nano devices simplify total system design and reduce cost and
design risk while increasing system reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 nano flash-
based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 nano FPGAs
cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors
occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection
and correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3 nano devices exhibit power characteristics similar to an ASIC, making them an
ideal choice for power-sensitive applications. ProASIC3 nano devices have only a very limited power-on
current surge and no high-current transition period, both of which occur on many FPGAs.
ProASIC3 nano devices also have low dynamic power consumption to further maximize power savings.
Advanced Flash Technology
ProASIC3 nano devices offer many benefits, including nonvolatility and reprogrammability through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A3PN250-Z2VQ100 | 功能描述:IC FPGA NANO 250K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| A3PN250-Z2VQ100I | 功能描述:IC FPGA NANO 250K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| A3PN250-Z2VQG100 | 功能描述:IC FPGA NANO 250K GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| A3PN250-Z2VQG100I | 功能描述:IC FPGA NANO 250K GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| A3PN250-ZVQ100 | 功能描述:IC FPGA NANO 250K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
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