参数资料
| 型号： | A4403GEUTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A 16QFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 9 V ~ 46 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 450kHz ~ 2MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 16-QFN（4x4） |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1273-6 |
A4403
(f) The total losses can now be estimated:
Valley Current Mode Control Buck Converter
(c) Diode capacitance turn-on loss (equation 23):
P TOTAL = P STAT + P DYN + P DIODECAP + P CTRL + P GATE . (26)
P DIODECAP =
150 × 10 –12 × 42 2 × 1 × 10 6
2
= 0.132 W
4. The thermal impedance required for the solution can now be
determined:
(d) Control losses (equation 24):
R
JA
=
T J – T A
P TOTAL
.
(27)
P CTRL = 0.004 × 42 = 0.168 W
(e) Gate charge losses (equation 25):
=
= 31°C/W
R
1.447
D (max) = = 0.09
Note that if a four-layer high thermal efficiency board is used, a
thermal impedance of around 30°C/W can be achieved.
Example
Given selected parameters:
V IN (min) = 42 V,
V OUT = 3.3 V at 3 A,
f SW = 1 MHz,
T A = 70°C,
Target junction temperature, T J = 115°C,
V f = 0.55 V, and
C DIODE = 150 pF, then:
(a) Switch static losses
Maximum duty cycle (equation 19):
3.3 + 0.55
42 + 0.55
R DS(on) of the buck switch (equation 20):
P GATE = 5 × 10 –9 × 1 × 10 6 × 42 = 0.21 W
(f) Total losses (equation 26):
P TOTAL = 0.433 + 0.504 + 0.132 + 0.168 + 0.21 = 1.447 W
Thermal impedance (equation 27):
115 – 70
JA
For this particular solution, a PCB with high thermal efficency is
required to ensure the junction temperature is kept below 115°C.
For maximum effectiveness, the PCB area underneath the thermal
pad of the A4403 should be flooded with copper. Several thermal
vias (say between 4 and 8) should be used to connect the thermal
pad to the internal ground plane. If possible, a further thermal
copper plane should be applied to the bottom side of the PCB and
connected to the thermal pad of the A4403 through the vias.
This calculation assumes no thermal influence from other compo-
nents. If possible, it is advisable to mount the recirculation diode
(D1) on the reverse side of the printed circuit board. Ensure low
impedance electrical connections are implemented between board
layers.
115 – 25 ? ?
?
R DS(on)TJ = 350 × 10 –3 ? ? 1 +
?
170 ? = 0.535 Ω
?
PCB Layout Guidelines The ground plane is largely dic-
tated by the thermal requirements of the previous section. The
ground-referenced power components should be referenced to a
Static loss for each switch (equation 21):
P STAT = 3 2 × 0.09 × 0.535 = 0.433 W
(b) Switch dynamic losses (equation 22):
star ground, located away from the A4403 to minimize ground
bounce issues.
A small, local, relatively quiet ground plane near the A4403
should be used for the ground-referenced support components,
P DYN = 42 ×
3
2
× 5 × 10 –9 × 1000 × 10 3 × 1.6 = 0.504 W
to minimize interference effects of ground noise from the power
circuitry. Figure 4 illustrates the recommended grounding archi-
tecture.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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