参数资料
| 型号： | A4403GEUTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A 16QFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 9 V ~ 46 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 450kHz ~ 2MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 16-QFN（4x4） |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1273-6 |
A4403
Valley Current Mode Control Buck Converter
.
(11)
I sat = I LOAD +
current, with perhaps some margin to allow for overloads, and
so forth.
? saturation current. The worst case maximum peak current
should not exceed the saturation current and indeed some mar-
gin should be allowed. The maximum peak current can be found
to ensure the saturation current level of the chosen inductor is
not exceeded:
I RIPPLE
2
It is important to ensure that, under worst-case conditions (mini-
mum input voltage, maximum load current, minimum inductance,
to reduce the bandwidth and therefore compromise the transient
response performance.
In general the output capacitance should not exceed 1000 μ F or
be less than 10 μ F, as this may cause a loop instability to occur.
The output ripple is largely determined by the output capacitance,
and the effects of ESR and ESL can largely be ignored assum-
ing good layout practice is observed. To help reduce the effects
of ESL it is a good idea to split the 20 μ F capacitance into two
separate 10 μ F components.
The output voltage ripple can be approximated to:
,
V RIPPLE ≈
and minimum switching frequency), that the minimum current
limit is not exceeded and in fact has some margin. The current
limit is measured at the valley level. The maximum current at the
valley is found from:
I RIPPLE
8 × f SW × C OUT
where I RIPPLE is as found in the Inductor section.
(13)
I valley
= I LOAD –
I RIPPLE
2
.
(12)
When using ceramic capacitors, due to the negligible heating
effects of the ESR, there is generally no need to consider the cur-
rent carrying capability. Also, the RMS current flowing into the
? V IN
?
× ? ?
– 1 ? ?
,
I rms =
(14)
V IN
? OUT
?
The minimum current limit threshold should be at least 20%
above this level.
Recommended inductor manufacturers and ranges are:
? Tayo Yuden: NR6045 series
? Sumida: CDR7D43MN series
Output Capacitor In the interests of size, cost, and perfor-
mance, this control architecture has been designed for ceramic
capacitors. It is imperative that ceramic X5R or X7R capacitors
are used. On no account should Y5V, Y5U, Z5U, or similar types
be used.
When using ceramic capacitors, another important consider-
ation is the E-field effects on the actual value of the capacitor.
To minimize the effects of the capacitance being reduced with
output voltage, it is recommended that the working voltage of the
capacitor be considerably more than the set output voltage. Check
with the vendor to obtain this information.
The output capacitor determines the output voltage ripple and is
used to close the control loop. As outlined in the Control Loop
section, the bandwidth has been optimized for an output capaci-
tance of 20 μ F.
If a particular application requires an extremely low output volt-
age, the output capacitor can be increased. Any increase will tend
output capacitor is extremely low.
Input Capacitor It is recommended that ceramic X5R or X7R
capacitors be used, or at least that they be used in conjunction
with some other capacitor technology; for example, aluminum
electrolytic. Note that the self-resonance of electrolytics tend to
occur in the 100s of kHz, therefore the effects of ESL become
apparent at switching frequencies in the region of 1 MHz.
The value of the input capacitance determines the amount of
ripple voltage that appears at the source terminals. If a system is
designed correctly, the input capacitor should supply the switch-
ing current minus the input average current during the on-time of
the power switch. During the off-time of the power switch, the
input capacitor is charged-up.
The RMS current that flows in the input capacitor can be found
from:
1/2
I OUT × V OUT
V
The amount of ripple voltage that appears across the input termi-
nals depends on: the amount of charge removed during the switch
on-time and the actual capacitor value. If a capacitor technology
such as an electrolytic is used, then the effects of ESR also have
to be considered.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
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