参数资料
型号: A4490EES-T
厂商: Allegro Microsystems Inc
文件页数: 12/17页
文件大小: 0K
描述: IC REG BUCK ADJ 1.5A TRPL 20QFN
标准包装: 92
类型: 降压(降压)
输出类型: 可调式
输出数: 3
输出电压: 可调
输入电压: 4.5 V ~ 34 V
PWM 型: 电流模式
频率 - 开关: 550kHz
电流 - 输出: 1.5A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
包装: 管件
供应商设备封装: 20-QFN 裸露焊盘(4x4)
配用: 620-1388-ND - BOARD EVAL FOR A4490
其它名称: A4490SES-T
A4490SES-T-ND
A4490
Triple Output Step-Down Switching Regulator
,
D(max) =
V BB (min) + V f
Again, there is generally no need to consider the heating effects
of the rms current flowing through the ESR. Also, the phase-
shifting of the input current drawn by each of the regulators helps
to reduce the overall rms current.
Flyback Diode This diode conducts during the switch off-time.
A Schottky diode is recommended to minimize both the forward
drop and switching losses.
The worst case dissipation occurs at maximum V BB , when the
duty cycle, D, is a minimum. The average current through the
diode can be found:
I DIODE(av) = I LOAD × (1 – D(min)) . (7)
The forward voltage drop, V f , can be found from the diode
characteristics by using the actual load current (not the average
current).
The static power dissipation can be found:
P STAT = I LOAD(av) × V f . (8)
It is also important to take into account the thermal rating of
the package, R θ JA , and the ambient temperature, to ensure that
enough heatsinking is provided to maintain the diode junction
temperature within the safe operating area for the device.
The following steps can be used as a guideline for determining a
suitable thermal solution. It should be noted that this process is
usually an iterative one to achieve the optimum solution. These
factors can be considered as follows:
Step 1. Estimate the maximum ambient temperature, T A (max) , of
the application.
Step 2. Define the maximum junction temperature, T J (max). Note
that the absolute maximum is 150°C.
Step 3. Determine the worst case power dissipation, P D (max).
The evaluation should consider these at maximum load and mini-
mum V BB . Contributors are switch static and dynamic losses, and
control losses. These are described in the following sections
Switch Static Losses The following steps can be used to
determine switch static losses:
Estimate the maximum duty cycle:
V REG + V f
(9)
where V f is the forward voltage drop of the Schottky diode under
the given load current.
R DS(on)TJ = R DS(on)25C ? ? 1 +
?
?
?
To minimize the heating effects from the A4490 on the diode and
vice-versa, it is recommended that the diode be mounted on the
reverse side of the printed circuit board.
Support Components POR capacitor (C11), charge pump
capacitor (C1), reservoir capacitor (C2) and VDD filter capacitor
Estimate the R DS(on) of the each regulator switch at the given
junction temperature:
? T J – 25 ?
? .
200
(10)
(C12) should be ceramic X5R or X7R.
Thermal Considerations
To ensure the A4490 operates in the safe operating area, which
effectively means restricting the junction temperature to less than
150°C, several checks should be made. The general approach
is to work out what thermal impedance (R ? JA ) is required to
maintain the junction temperature at a given level, for a particular
power dissipation.
Another factor worth considering is that other power dissipating
components on the system PCB may influence the thermal per-
Note that if the V BB range is restricted to between 4.5 and 5.5 V,
the R DS(on) increases. For example, the R DS(on) at 25°C with a
V BB greater than 6 V is 450 m Ω typical, as stated in the Electri-
cal Characteristics table. Under the same temperature conditions,
with the V BB = 4.5 V, the R DS(on) is 560 m Ω typical. For VBB
voltages between 4.5 and 6 V, the R DS(on) can be found by linear
approximation. For more information on operating the A4490
between a V BB voltage of 4.5 and 5.5 V, see the Power Configu-
rations section.
The static loss for each switch can be determined:
formance of the A4490. For example, the power loss contribution
from the recirculation diode and the sense resistor may cause the
junction temperature of the A4490 to be higher than expected.
P STAT = I LOAD2 × D(max) × R DS(on)TJ ,
where I LOAD is the load for that particular regulator channel.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
(11)
12
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