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| 型号： | A4490EES-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 9/17页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1.5A TRPL 20QFN |
| 标准包装： | 92 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 3 |
| 输出电压： | 可调 |
| 输入电压： | 4.5 V ~ 34 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 550kHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 配用： | 620-1388-ND - BOARD EVAL FOR A4490 |
| 其它名称： | A4490SES-T A4490SES-T-ND |
A4490
Triple Output Step-Down Switching Regulator
R 1 = R 2 ? ? REG1
– 1 ? ?
When theV BB voltage starts to fall below the undervoltage warn-
ing level, V BBUV(por) , of 3.6 V typical, the PORZ flag resets.
This gives advance warning to the system controller that the V BB
voltage is falling. Note that this feature is only guaranteed when
VDD is supplied externally. During this interval, the three switch-
ers continue to operate.
While V BB falls further, the VCP supply also tends to fall, which
degrades the drive voltage to the series switches. In addition,
the higher voltage rails start to fall out of regulation first, as the
corresponding maximum duty cycle (D max ) for these particular
converters is reached.
The regulators that have the lower output voltages achieve some
level of steady state, before the A4490 powers down when all
of the corresponding V BB undervoltage thresholds have been
reached. For example, it may be possible for a 1 V output to
continue to operate down to a V BB of 3.4 V typical, if the VDD
supply is derived externally. The extent of this effect depends on
a myriad of factors, including input and output filter capacitance,
output loads, gate drive amplitude, MOSFET R DS(on) , and so
forth.
Powering Up and Down with Enable Referring to figure 2,
V BB is present and the UVLO start-up thresholds, V BBUV(su)
and V BBCPUV(su) have been reached. Each of the regulators are
enabled in turn. Initially, VREG1 is enabled and is brought-up
under the control of the soft start circuit (t SS ). Before VREG1
reaches 85% FB1, VREG2 is enabled and is brought-up under a
separate soft start control.
When both regulators have reached their respective 85% FB
thresholds, the power-on-reset (POR) timer is initiated. Note that
the POR timer is only enabled after all of the enabled regulators
reach their corresponding 85% FB levels. After the power-on-
reset time, t POR , has elapsed, if the FB levels of VREG1 and
VREG2 are not below their respective 80% FB levels, then the
PORZ signal will go high.
At some point later, if VREG3 is enabled, then the PORZ is
reset and VREG3 is brought-up under the control of the soft start
circuit. When the 85% FB3 threshold is reached, the POR timer
is initiated. After t POR has elapsed, if all the FB levels are above
their respective 80% FB levels, then the PORZ signal will go
high.
Note that if any regulator channel is not enabled, the channel
will not influence PORZ. To avoid multiple signal changes of the
PORZ signal, it is recommended that the system be designed such
that all three regulator channels are within specification before
t POR has elapsed.
If any regulator channel drops below 80% FB, the PORZ signal
will be reset. If the voltage then recovers to within 85% FB, the
POR timer is initiated again. Note that a soft start is not initiated
when the feedback voltage drops below the 80% FB level. This is
to allow a rapid auto-restart in the event of an overload or similar
fault. If a soft start is required, it is recommended that on receipt
of the PORZ reset signal, the system controller disables and then
re-enables the relevant regulator channels again. As soon as the
last regulator is disabled the PORZ signal is reset.
Power on Reset The power-on-reset duration, t POR , is deter-
mined by selecting an appropriate capacitor connected to the
CPOR pin. The value of t POR can be determined by the following
formula:
t POR = 2.131 ×10 5 × C POR . (1)
The PORZ output goes high when both V BB is above the under-
voltage warning levels, and the FB pins of the regulators that are
enabled are > 85% of the V REG voltage.
Because the external capacitor is charged via a 5 μ A current
source, care must be taken in the layout to avoid additional leak-
age paths. The capacitor should be positioned adjacent to the
CPOR pin, and the ground connection to the A4490 GND pin
should be as short as possible.
It is recommended that the t POR period be set to exceed the
start-up phases of all three regulators, to avoid the possibility of
multiple triggerings of the PORZ output.
Output Voltage Selection The output voltage on each of the
three regulators is set by the following relationship, shown here
for the VREG1 channel:
? V ?
, (2)
? V FB ?
where R2 (connected between GND and the FB1 pin) should
be a value between 4.7 and 12 k Ω . R1 is connected between the
output rail and the FB1 pin. V REG1 is the set output regulator
voltage. V FB is the reference voltage.
The tolerances of the feedback resistors influence the voltage set-
point. It is therefore important to consider the tolerance selection
when targeting an overall regulation figure.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
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| A4490EESTRT | 制造商:ALLEGRO 功能描述:Pb Free |
| A4490EESTR-T | 功能描述:IC REG BUCK ADJ 1.5A TRPL 20QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON（1.45x1） 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2 |
| A4491 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Designed to provide the power supply requirements of printers, office automation, industrial, and portable equipment, the A4491 provides three high current, |
| A4491EESTR-T | 功能描述:IC REG BUCK ADJ 2.2A TRPL 20QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:50 系列:- 类型:升压（升压） 输出类型:可调式 输出数:1 输出电压:5 V ~ 25 V 输入电压:2.3 V ~ 5.5 V PWM 型:电流模式 频率 - 开关:600kHz，1.2MHz 电流 - 输出:1A 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装:管件 供应商设备封装:8-MSOP |
| A4492 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Designed to provide the power supply requirements for automotive applications, the A4492 provides three high current, high performance, switching regulator outputs with independent soft start. |
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