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参数资料
| 型号： | A4490EES-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 13/17页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1.5A TRPL 20QFN |
| 标准包装： | 92 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 3 |
| 输出电压： | 可调 |
| 输入电压： | 4.5 V ~ 34 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 550kHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 配用： | 620-1388-ND - BOARD EVAL FOR A4490 |
| 其它名称： | A4490SES-T A4490SES-T-ND |
A4490
Triple Output Step-Down Switching Regulator
Switch Dynamic Losses The following can be used to deter-
(a) Switch static losses
30 10 –9
P DYN = V BB (min)
2
V REG1 duty cycle, D 1 =
= 0.84
V REG2 duty cycle, D 2 = = 0.58
V REG3 duty cycle, D 3 = = 0.34
mine switch dynamic losses:
Both turn on and turn off losses can be estimated:
I LOAD
f SW
,
(12)
5+0.4
6+0.4
3.3+0.4
6+0.4
1.8+0.4
6+0.4
? ?
R DS(on)TJ = 450×10 –3 ? ? 1 +
? = 0.653 Ω
?
?
?
where f SW is the switching frequency.
Control Losses The following steps can be used to determine
control losses:
The R DS(on) of each switch can be found:
1 15 – 25
200
P VBB = I BBON × V BB ,
(13)
The static loss of each switch can be found:
P STAT1 = 1 2 × 0.84 × 0.653 = 0.55 W
where I BBON is the quiescent current assuming all three regulators
are on.
P STAT2 = 1 2 × 0.58 × 0.653 = 0.379 W
P STAT3 = 0.8 2 × 0.34 × 0.653 = 0.14 W
P DYN1 = 6
30 10 –9
P DYN2 = 6
30 10 –9
P DYN3 = 6
30 10 –9
P VDD = I VDD × V DD ,
where I VDD and is the quiescent current on VDD.
Total Losses The total losses can now be estimated:
P TOTAL = P STAT1 + P STAT2 + P STAT2
(14)
(b) Switch dynamic losses
1
2
1
2
0. 8
2
500 10 3 = 0.045 W
500 10 3 = 0.045 W
500 10 3 = 0.036 W
+ P DYN1 + P DYN2 + P DYN3
+ P VBB + P VDD . (15)
Thermal Impedance The thermal impedance required for the
solution can now be determined:
(c) Control losses
P VBB = 0.005 × 6 = 0.03 W
P VDD = 0.001 × 3.3 = 0.003 W
(d) The total power dissipation can now be found:
P TOTAL = 0.55 + 0.379 + 0.14 + 0.045
R
JA
=
T J – T A
P TOTAL
.
(16)
+ 0.045 + 0.036 + 0.03 + 0.003 = 1.228 W
(e) The thermal impedance required for the solution can be
R JA = = 36.6 °C/W
Example
Selected parameters:
V BB (min) = 6 V
V REG1 = 5 V at 1 A
V REG2 = 3.3 V at 1 A
V REG3 = 1.8 V at 800 mA
T A = 70°C
T J = 115°C
V f = 0.4 V
found:
115 – 70
1.228
For this particular solution a high thermal efficiency board is
required to ensure the junction temperature is kept below 115°C.
For maximum effectiveness, the PCB pad area underneath the
thermal pad of the A4490 should be exposed copper. Several
thermal vias (say between 4 and 8) should be used to connect
the thermal pad to the internal ground plane. If possible, an
additional thermal copper plane should be applied to the bottom
side of the PCB and connected to the thermal pad of the A4490
through the vias.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
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| A4490EESTRT | 制造商:ALLEGRO 功能描述:Pb Free |
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