- 您现在的位置：买卖IC网 > PDF目录379534 > A54SX08P-PQ208M (Electronic Theatre Controls, Inc.) 54SX Family FPGAs PDF资料下载
参数资料
| 型号： | A54SX08P-PQ208M |
| 厂商： | Electronic Theatre Controls, Inc. |
| 元件分类： | FPGA |
| 英文描述： | 54SX Family FPGAs |
| 中文描述： | 54SX家庭的FPGA |
| 文件页数： | 19/57页 |
| 文件大小： | 415K |
| 代理商： | A54SX08P-PQ208M |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页
v3.1
19
5 4 S X F a m ily F P G A s
G uide line s for C a lc ula t ing P ow e r
C ons um pt ion
The following guidelines are meant to represent worst-case
scenarios so that they can be generally used to predict the
upper limits of power dissipation. These guidelines are as
follow:
Logic Modules (m)
Inputs Switching (n)
Outputs Switching (p)
First Routed Array Clock Loads (q
1
)
S a m ple P ow e r C a lc ula t ion
One of the designs used to characterize the A54SX family
was a 528 bit serial in serial out shift register. The design
utilized 100%of the dedicated flip-flops of an A54SX16P
device. A pattern of 0101… was clocked into the device at
frequencies ranging from 1 MHz to 200 MHz. Shifting in a
series of 0101… caused 50%of the flip-flops to toggle from
low to high at every clock cycle.
Follow the steps below to estimate power consumption. The
values provided for the sample calculation below are for the
shift register design above. This method for estimating
power consumption is conservative and the actual power
consumption of your design may be less than the estimated
power consumption.
The total power dissipation for the 54SX family is the sum of
the AC power dissipation and the DC power dissipation.
P
Total
= P
AC
(dynamic power) + P
DC
(static power)
(5)
A C P ow e r Dis s ipa t ion
P
AC
= P
Module
+ P
RCLKA Net
+ P
RCLKB Net
+ P
HCLK Net
+
P
Output Buffer
+ P
Input Buffer
P
AC
= V
CCA2
* [(m * C
EQM
* f
m
)
Module
+
(n * C
EQI
* f
n
)
Input Buffer
+ (p * (C
EQO
+ C
L
) * f
p
)
Output
Buffer
+
(0.5 * (q
1
* C
EQCR
* f
q1
) + (r
1
* f
q1
))
RCLKA
+
(0.5 * (q
2
* C
EQCR
* f
q2
)+ (r
2
* f
q2
))
RCLKB
+
(0.5 * (s
1
* C
EQHV
* f
s1
) + (C
EQHF
* f
s1
))
HCLK
]
Step #1:
Define Terms Used in Formula
V
CCA
Module
Number of logic modules switching at f
m
(Used 50%
Average logic modules switching rate
f
m
(MHz) (Guidelines: f/10)
Module capacitance C
EQM
(pF)
Input Buffer
Number of input buffers switching at f
n
Average input switching rate f
n
(MHz)
(Guidelines: f/5)
Input buffer capacitance C
EQI
(pF)
Output Buffer
Number of output buffers switching at f
p
Average output buffers switching rate
f
p
(MHz) (Guidelines: f/10)
Output buffers buffer Capacitance C
EQO
(pF) C
EQO
4.7
Output Load capacitance C
L
(pF)
RCLKA
Number of Clock loads q
1
Capacitance of routed array clock (pF)
Average clock rate (MHz)
Fixed capacitance (pF)
RCLKB
Number of Clock loads q
2
Capacitance of routed array clock (pF)
Average clock rate (MHz)
Fixed capacitance (pF)
HCLK
Number of Clock loads
Variable capacitance of dedicated
array clock (pF)
Fixed capacitance of dedicated
array clock (pF)
Average clock rate (MHz)
(6)
(7)
= 20%of modules
= #inputs/4
= #output/4
= 20%of register
cells
Second Routed Array Clock Loads (q
2
) = 20%of register
cells
Load Capacitance (C
L
)
Average Logic Module Switching Rate
(f
m
)
Average Input Switching Rate (f
n
)
Average Output Switching Rate (f
p
)
Average First Routed Array Clock Rate
(f
q1
)
Average Second Routed Array Clock
Rate (f
q2
)
Average Dedicated Array Clock Rate
(f
s1
)
Dedicated Clock Array clock loads (s
1
) = 20%of regular
= 35 pF
= f/10
= f/5
= f/10
= f/2
= f/2
= f
modules
3.3
m
264
f
m
20
C
EQM
4.0
n
f
n
1
40
C
EQI
3.4
p
f
p
1
20
C
L
35
q
1
C
EQCR
1.6
f
q1
r
1
528
200
138
q
2
C
EQCR
1.6
f
q2
r
2
0
0
138
s
1
C
EQHV
0.615
0
C
EQHF
96
f
s1
0
相关PDF资料 |
PDF描述 |
|---|---|
| A54SX08P-PQ208PP | LM1881 Video Sync Separator; Package: SOIC NARROW; No of Pins: 8 |
| A54SX08P-TQ208 | LM1881 Video Sync Separator; Package: MDIP; No of Pins: 8; Qty per Container: 40; Container: Rail |
| A54SX08P-TQ208I | LM1894 Dynamic Noise Reduction System DNR®; Package: SOIC NARROW; No of Pins: 14; Qty per Container: 55; Container: Rail |
| A54SX08P-TQ208M | 54SX Family FPGAs |
| A54SX08P-TQ208PP | 54SX Family FPGAs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A54SX08P-PQ208PP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
| A54SX08-PQ208 | 功能描述:IC FPGA SX 12K GATES 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A54SX08-PQ208I | 功能描述:IC FPGA SX 12K GATES 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A54SX08-PQ208M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
| A54SX08-PQ208PP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
发布紧急采购，3分钟左右您将得到回复。