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| 型号： | A54SX08P-PQ208M |
| 厂商： | Electronic Theatre Controls, Inc. |
| 元件分类： | FPGA |
| 英文描述： | 54SX Family FPGAs |
| 中文描述： | 54SX家庭的FPGA |
| 文件页数： | 5/57页 |
| 文件大小： | 415K |
| 代理商： | A54SX08P-PQ208M |
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v3.1
5
5 4 S X F a m ily F P G A s
The C-cell implements a range of combinatorial functions
up to 5-inputs (
Figure3
). Inclusion of the DB input and its
associated inverter function dramatically increases the
number of combinatorial functions that can be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the SX
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to integrate
a 3-input exclusive-OR function into a single C-cell. This
facilitates construction of 9-bit parity-tree functions with 2
ns propagation delays. At the same time, the C-cell
structure is extremely synthesis friendly, simplifying the
overall design and reducing synthesis time.
C hip A rc hit e c t ure
The SX family’s chip architecture provides a unique
approach to module organization and chip routing that
delivers the best register/logic mix for a wide variety of new
and emerging applications.
Module Org a niz a t ion
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called
Clusters
. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance, Actel
has further organized these modules into
SuperClusters
(
Figure4 on page6
). SuperCluster 1 is a two-wide grouping
of Type 1 clusters. SuperCluster 2 is a two-wide group
containing one Type 1 cluster and one Type 2 cluster. SX
devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
significantly more combinatorial logic than flip-flops.
Figure 2
R-Cell
Figure 3
C-Cell
Direct
Connect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS
CKP
CLRB
PSETB
Y
D
Q
Routed
Data Input
S0
S1
D0
D1
D2
D3
DB
A0
B0
A1
B1
Sa
Sb
Y
相关PDF资料 |
PDF描述 |
|---|---|
| A54SX08P-PQ208PP | LM1881 Video Sync Separator; Package: SOIC NARROW; No of Pins: 8 |
| A54SX08P-TQ208 | LM1881 Video Sync Separator; Package: MDIP; No of Pins: 8; Qty per Container: 40; Container: Rail |
| A54SX08P-TQ208I | LM1894 Dynamic Noise Reduction System DNR®; Package: SOIC NARROW; No of Pins: 14; Qty per Container: 55; Container: Rail |
| A54SX08P-TQ208M | 54SX Family FPGAs |
| A54SX08P-TQ208PP | 54SX Family FPGAs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A54SX08P-PQ208PP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
| A54SX08-PQ208 | 功能描述:IC FPGA SX 12K GATES 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A54SX08-PQ208I | 功能描述:IC FPGA SX 12K GATES 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A54SX08-PQ208M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
| A54SX08-PQ208PP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
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