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参数资料
| 型号： | ACS8946 |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC48 |
| 封装： | 7 X 7 MM, QFN-48 |
| 文件页数： | 38/40页 |
| 文件大小： | 663K |
| 代理商： | ACS8946 |
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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 7
www.semtech.com
ACS8946 JAM PLL
Note...A= Analog, I = Input, O = Output, P = Power, LVTTL/LVCMOSU = LVTTL/LVCMOS input with pull-up resistor, LVTTL/LVCMOSD =
LVTTL/LVCMOS input with pull-down resistor.
33
AUTO_SEL
I
LVTTL/
LVCMOSD
Used in combination with pin 32, SEL_CLK2, to select automatic switching mode, as
described in Table 4.
35
VCP
A
Analog
Connection for external loop filter components. This is the differential control voltage
input to the internal VCO and the internal differential charge pump output up to a level of
210
A.
36
VCN
A
Analog
Connection for external loop filter components. This is the differential control voltage
input to the internal VCO and the internal differential charge pump output up to a level of
210
A.
40
RESETB
I
LVTTL/
LVCMOSU
Schmitt
Trigger
Active low reset signal with pull up and Schmitt type input. Used to apply an active-low
Power-on Reset (POR) signal during system initialization. Should be connected via a
capacitor to ground.
41
SYNCP
I
LVPECL
Additional differential input (2 kHz or 8 kHz) where the Sync signal on this input is
sampled and resynchronized by clock output OUT1. The resynchronization can be
configured via CFG_IN4 and CFG_IN5 to be with the rising or falling edge of output OUT1;
see Table 12. Will also accept CML or LVDS signal types when used in conjunction with
42
SYNCN
I
LVPECL
Additional differential input (2 kHz or 8 kHz) where the Sync signal on this input is
sampled and resynchronized by clock output OUT1. The resynchronization can be
configured via CFG_IN4 and CFG_IN5 to be with the rising or falling edge of output OUT1;
see Table 12. Will also accept CML or LVDS signal types when used in conjunction with
44
SYNC_OUT
O
LVTTL/
LVCMOS
A sampled and therefore lower jitter and resynchronized version of the SYNC signal
selected from the SYNC1 input. The clock selected on OUT1 (see pins 2 and 3) is used to
perform the resynchronization. The resynchronization can be configured to be with the
rising or falling edge of output OUT1; see Table 12. The maximum output frequency on
OUT1 = 77.76 MHz when the Sync function is used.
45
RATE2A
I
LVTTL/
LVCMOSD
Inputs to control the frequency of the signal produced on pins 5 (OUT2P) and 6 (OUT2N).
See Table 11.
46
RATE2B
I
LVTTL/
LVCMOSD
Inputs to control the frequency of signal that is produced on pins 5 (OUT2P) and 6
(OUT2N). See Table 11.
47
RATE1A
I
LVTTL/
LVCMOSD
Inputs to control the frequency of signal that is produced on pins 2 (OUT1P) and 3
(OUT1N). See Table 11.
48
RATE1B
I
LVTTL/
LVCMOSD
Inputs to control the frequency of signal that is produced on pins 2 (OUT1P) and 3
(OUT1N). See Table 11.
Table 3 Functional Pins (cont...)
Pin No.
Symbol
I/O
Type
Description
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